性能最好的鉴频鉴相器芯片
时间: 2023-11-06 13:04:30 浏览: 183
基于FPGA的一种新型数字鉴频鉴相器的设计.pdf
根据引用的内容,可以得知在TSMC 0.18μm CMOS工艺中设计的一款应用在芯片级铷原子钟3.4 GHz激励源中的鉴频鉴相器和电荷泵电路,该鉴频鉴相器由两个边沿触发、带复位的D触发器和一个与门组成。这款设计的鉴频鉴相器采用了边沿触发的设计,同时还增加了一个延时单位以消除死区。然而,没有提到该芯片性能是否最好,因此无法确定哪款鉴频鉴相器芯片具有最好的性能。<span class="em">1</span><span class="em">2</span><span class="em">3</span>
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