用vhdl语言写16-4优先编码器

好的，以下是用 VHDL 语言编写的 16-4 优先编码器的代码：

entity priority_encoder is
    Port ( input_vector : in  std_logic_vector(15 downto 0);
           output_vector : out  std_logic_vector(3 downto 0));
end priority_encoder;

architecture Behavioral of priority_encoder is
begin
    process(input_vector)
    begin
        case input_vector is
            when "0000000000000001" => output_vector <= "0001";
            when "0000000000000010" => output_vector <= "0010";
            when "0000000000000100" => output_vector <= "0011";
            when "0000000000001000" => output_vector <= "0100";
            when "0000000000010000" => output_vector <= "0101";
            when "0000000000100000" => output_vector <= "0110";
            when "0000000001000000" => output_vector <= "0111";
            when "0000000010000000" => output_vector <= "1000";
            when "0000000100000000" => output_vector <= "1001";
            when "0000001000000000" => output_vector <= "1010";
            when "0000010000000000" => output_vector <= "1011";
            when "0000100000000000" => output_vector <= "1100";
            when "0001000000000000" => output_vector <= "1101";
            when "0010000000000000" => output_vector <= "1110";
            when "0100000000000000" => output_vector <= "1111";
            when others => output_vector <= "0000";
        end case;
    end process;
end Behavioral;

这里使用了一个 `process` 进程，通过 `case` 语句对输入的 16 位二进制数进行判断，根据不同情况给出相应的 4 位优先编码输出。如果输入的数不在编码器能够处理的范围内，则输出全 0。