24位booth 乘法器Verilog 代码和testbench

以下是24位booth乘法器的Verilog代码和testbench：

Verilog代码：

module booth_multiplier(input signed [23:0] multiplicand,
                        input signed [23:0] multiplier,
                        output signed [47:0] product);

reg [47:0] product_reg;
reg [23:0] multiplicand_reg;
reg [23:0] multiplier_reg;
reg [1:0] count_reg;

assign product = product_reg;

always @(posedge clk) begin
    if (rst) begin
        product_reg <= 0;
        multiplicand_reg <= 0;
        multiplier_reg <= 0;
        count_reg <= 0;
    end
    else begin
        product_reg <= {product_reg[46:0], multiplicand_reg[0]};
        multiplicand_reg <= {multiplicand_reg[22:0], multiplicand_reg[23]};
        count_reg <= count_reg + 1;
        if (count_reg[1:0] == 2'b10) begin
            multiplier_reg <= {multiplier_reg[22:0], multiplier_reg[23]};
        end
        else if (count_reg[1:0] == 2'b01) begin
            multiplier_reg <= {multiplier_reg[22:0], multiplier_reg[23]} - multiplier;
        end
    end
end

endmodule

testbench代码：

module booth_multiplier_tb();

reg signed [23:0] multiplicand;
reg signed [23:0] multiplier;
wire signed [47:0] product;

booth_multiplier dut(.multiplicand(multiplicand),
                     .multiplier(multiplier),
                     .product(product));

initial begin
    $dumpfile("booth_multiplier_tb.vcd");
    $dumpvars(0, booth_multiplier_tb);
end

always #10 multiplicand = $random;
always #15 multiplier = $random;

initial begin
    #1000 $finish;
end

endmodule