vhdl设计pwm信号发生器

下面是一个简单的VHDL代码，用于实现一个PWM信号发生器：

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity pwm_generator is
    port (
        clk     : in  std_logic;
        reset   : in  std_logic;
        duty    : in  std_logic_vector(7 downto 0);
        pwm_out : out std_logic
    );
end entity;

architecture rtl of pwm_generator is
    signal count : unsigned(7 downto 0) := (others => '0');
begin
    process(clk, reset)
    begin
        if reset = '1' then
            count <= (others => '0');
            pwm_out <= '0';
        elsif rising_edge(clk) then
            count <= count + 1;
            if count < unsigned(duty) then
                pwm_out <= '1';
            else
                pwm_out <= '0';
            end if;
        end if;
    end process;
end architecture;

该代码使用一个计数器来生成PWM信号。计数器在时钟上升沿时递增，当计数器小于占空比参数duty时，PWM输出为高电平，否则为低电平。当重置信号变为高电平时，计数器被清零并且PWM输出被强制置为低电平。