请给出verilog，三段式状态机模板

以下是一个简单的三段式状态机的 Verilog 代码模板：

module state_machine (
    input clk,
    input rst,
    input [n-1:0] input_signal,
    output reg [m-1:0] output_signal
);

// Declare state enum
typedef enum logic [1:0] {
    STATE_IDLE,
    STATE_WAIT,
    STATE_PROCESS
} state_t;

// Declare state and next_state variables
state_t state, next_state;

// Declare state register
reg [1:0] state_reg;

// Declare output register
reg [m-1:0] output_reg;

always @(posedge clk or posedge rst)
begin
    if (rst) begin
        // Reset state and output registers
        state_reg <= STATE_IDLE;
        output_reg <= 'b0;
    end
    else begin
        // Update state and output registers based on current state
        state_reg <= next_state;
        output_reg <= output_signal;
    end
end

always @(*)
begin
    // Set next_state based on current state and input signal
    case (state_reg)
        STATE_IDLE:
            if (input_signal == 'b1) begin
                next_state = STATE_WAIT;
            end
            else begin
                next_state = STATE_IDLE;
            end
        STATE_WAIT:
            if (input_signal == 'b0) begin
                next_state = STATE_PROCESS;
            end
            else begin
                next_state = STATE_WAIT;
            end
        STATE_PROCESS:
            next_state = STATE_IDLE;
    endcase
end

// Assign output_signal to output_reg
assign output_signal = output_reg;

endmodule

其中，`n` 和 `m` 分别是输入和输出信号的位宽。在 `always @(*)` 语句块中，我们可以根据当前状态和输入信号来确定下一个状态 `next_state`。在 `always @(posedge clk or posedge rst)` 语句块中，我们可以根据 `next_state` 来更新状态寄存器 `state_reg` 和输出寄存器 `output_reg`。最后，我们使用 `assign` 语句将 `output_reg` 赋值给 `output_signal`。