Verilog设计一个博物馆投币售票机控制系统

module ticket_machine(
input clk, //时钟信号
input reset, //复位信号
input coin, //投币信号
input btn, //购票按钮信号
output reg ticket //售票信号
);

reg [1:0] state; //状态寄存器

parameter idle = 2'b00; //空闲状态
parameter coin_inserted = 2'b01; //已投币状态
parameter ticket_sold = 2'b10; //售票状态

always @(posedge clk or posedge reset) begin
if (reset) begin
state <= idle; //复位时进入空闲状态
ticket <= 0; //清空售票信号
end else begin
case (state)
idle: begin
if (coin) begin
state <= coin_inserted; //进入已投币状态
ticket <= 0; //清空售票信号
end else begin
state <= idle; //保持空闲状态
ticket <= 0; //清空售票信号
end
end
coin_inserted: begin
if (btn) begin
state <= ticket_sold; //进入售票状态
ticket <= 1; //设置售票信号
end else if (coin) begin
state <= coin_inserted; //保持已投币状态
ticket <= 0; //清空售票信号
end else begin
state <= idle; //回到空闲状态
ticket <= 0; //清空售票信号
end
end
ticket_sold: begin
state <= idle; //售票后回到空闲状态
ticket <= 0; //清空售票信号
end
endcase
end
end

endmodule