写出一个三位全加器verilog代码

以下是一个三位全加器的 Verilog 代码：

module full_adder_3bit(A, B, Cin, Sum, Cout);
  input [2:0] A;
  input [2:0] B;
  input Cin;
  output [2:0] Sum;
  output Cout;

  wire c1, c2;

  // First bit addition
  full_adder FA1(.A(A[0]), .B(B[0]), .Cin(Cin), .Sum(Sum[0]), .Cout(c1));

  // Second bit addition
  full_adder FA2(.A(A[1]), .B(B[1]), .Cin(c1), .Sum(Sum[1]), .Cout(c2));

  // Third bit addition
  full_adder FA3(.A(A[2]), .B(B[2]), .Cin(c2), .Sum(Sum[2]), .Cout(Cout));
endmodule

module full_adder(A, B, Cin, Sum, Cout);
  input A;
  input B;
  input Cin;
  output Sum;
  output Cout;

  assign Sum = A ^ B ^ Cin;
  assign Cout = (A & B) | (Cin & (A ^ B));
endmodule

这个三位全加器模块使用了三个单独的 full_adder 模块来完成三个位的加法。对于每个位的加法，都需要将前一位的进位作为当前位的进位输入。最终的结果由 Sum 输出，进位由 Cout 输出。