Consider two 4-bit binary numbers A and B. Bits of A are a3, a2, a1, and a0, and bits of B are b3, b2, b1, and b0. A is greater than B if a3 is 1 and b3 is 0, but if a3 and b3 are the same, then if a2 is 1 and b2 is 0, we can determine that A is greater than B. This evaluation continues until a0 and b0 are considered. If a0 and b0 are equal then A and B are equal. Using discrete gates and Verilog gate primitives build a 4-bit comparator that generates a 1 on its GT output when its 4-bit input A is greater than its B input, and a 1 on its EQ output when A and B are equal. Use the generate statement and other Verilog iterative logic support structures.

Here's one possible implementation of a 4-bit comparator in Verilog:

module comparator(A, B, GT, EQ);
  input [3:0] A, B;
  output GT, EQ;

  wire [3:0] greater;
  assign greater[3] = (A[3] == 1) && (B[3] == 0);
  assign greater[2] = (A[3] == B[3]) && (A[2] == 1) && (B[2] == 0);
  assign greater[1] = (A[3] == B[3]) && (A[2] == B[2]) && (A[1] == 1) && (B[1] == 0);
  assign greater[0] = (A[3] == B[3]) && (A[2] == B[2]) && (A[1] == B[1]) && (A[0] == 1) && (B[0] == 0);

  assign GT = greater[3] || greater[2] || greater[1] || greater[0];
  assign EQ = (A == B);
endmodule

In this implementation, we first create a wire `greater` that stores whether each bit of A is greater than the corresponding bit of B according to the rules specified in the problem statement. We then combine these results using logical OR to determine if A is overall greater than B.

We also use the equality operator `==` to check if A and B are equal, and assign the result to the wire `EQ`.

Note that this implementation makes use of the `generate` statement implicitly by using the array index notation to generate the logic for each bit of the `greater` wire.