veilog实现两个16bits*16bits矩阵的有符号乘法的testbench

下面是一个简单的Verilog testbench，用于测试两个16位带符号矩阵的乘法模块：

module testbench();

  // Parameters
  parameter WIDTH = 16;
  parameter SIZE = 16;

  // Inputs
  reg [WIDTH-1:0] A [SIZE-1:0];
  reg [WIDTH-1:0] B [SIZE-1:0];

  // Outputs
  wire [WIDTH*2-1:0] result [SIZE-1:0];

  // Instantiate the design under test
  mult_matrix_16x16_with_sign mult_matrix_16x16_with_sign(
    .A(A),
    .B(B),
    .result(result)
  );

  // Initialize inputs
  initial begin
    // Initialize A with some random values
    for (int i=0; i<SIZE; i=i+1) begin
      A[i] = $random;
    end

    // Initialize B with some random values
    for (int i=0; i<SIZE; i=i+1) begin
      B[i] = $random;
    end
  end

  // Print the input matrix
  initial begin
    $display("Input Matrix A:");
    for (int i=0; i<SIZE; i=i+1) begin
      for (int j=0; j<SIZE; j=j+1) begin
        $write("%d ", A[i][j]);
      end
      $write("\n");
    end

    $display("Input Matrix B:");
    for (int i=0; i<SIZE; i=i+1) begin
      for (int j=0; j<SIZE; j=j+1) begin
        $write("%d ", B[i][j]);
      end
      $write("\n");
    end
  end

  // Print the output matrix
  initial begin
    #10; // Wait some time for the design to compute the result
    $display("Result Matrix:");
    for (int i=0; i<SIZE; i=i+1) begin
      for (int j=0; j<SIZE; j=j+1) begin
        $write("%d ", result[i][j*WIDTH*2 +: WIDTH]);
      end
      $write("\n");
    end
  end

endmodule

请注意，此测试台仅适用于仿真，因此我们需要编写另一个模块来实现实际的硬件设计。