在VHDL用IF和when-else语句编写1位二进制全加器

可以使用 IF 和 when-else 语句编写 1 位二进制全加器，代码如下：

entity full_adder is
  port (
    a : in std_logic;
    b : in std_logic;
    c : in std_logic;
    sum : out std_logic;
    carry : out std_logic
  );
end full_adder;

architecture behavioral of full_adder is
begin
  process(a, b, c)
  begin
    if (a = '0' and b = '0' and c = '0') then
      sum <= '0';
      carry <= '0';
    elsif (a = '0' and b = '0' and c = '1') then
      sum <= '1';
      carry <= '0';
    elsif (a = '0' and b = '1' and c = '0') then
      sum <= '1';
      carry <= '0';
    elsif (a = '0' and b = '1' and c = '1') then
      sum <= '0';
      carry <= '1';
    elsif (a = '1' and b = '0' and c = '0') then
      sum <= '1';
      carry <= '0';
    elsif (a = '1' and b = '0' and c = '1') then
      sum <= '0';
      carry <= '1';
    elsif (a = '1' and b = '1' and c = '0') then
      sum <= '0';
      carry <= '1';
    elsif (a = '1' and b = '1' and c = '1') then
      sum <= '1';
      carry <= '1';
    end if;
  end process;
end behavioral;

在 process 中使用 IF 和 when-else 语句，根据输入的三个信号 a、b、c 的不同情况，计算出对应的 sum 和 carry 信号，输出到端口上。其中，sum 表示两个输入和进位的和，carry 表示两个输入和进位的进位信号。