用vhdl语言写一段模十计数器代码

library ieee;
use ieee.std_logic_1164.all;

entity mod10_counter is
port (
clk : in std_logic;
reset : in std_logic;
q : out std_logic_vector(3 downto 0)
);
end mod10_counter;

architecture behavior of mod10_counter is
begin
process (clk, reset)
variable count : integer range 0 to 9 := 0;
begin
if (reset = '1') then
count := 0;
q <= "0000";
elsif (rising_edge(clk)) then
if (count = 9) then
count := 0;
q <= "0000";
else
count := count + 1;
q <= std_logic_vector(to_unsigned(count, 4));
end if;
end if;
end process;
end behavior;

-- 测试用例
library ieee;
use ieee.std_logic_1164.all;

entity mod10_counter_test is
end mod10_counter_test;

architecture behavior of mod10_counter_test is
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal q : std_logic_vector(3 downto 0);
begin
uut : entity work.mod10_counter
port map (
clk => clk,
reset => reset,
q => q
);

clk_process : process
begin
while true loop
clk <= not clk;
wait for 5 ns;
end loop;
end process;

reset_process : process
begin
reset <= '1';
wait for 10 ns;
reset <= '0';
wait for 100 ns;
reset <= '1';
wait for 10 ns;
reset <= '0';
wait;
end process;

assert_0 : process
begin
wait until rising_edge(clk);
assert q = "0000" report "Error: q = " & to_string(q) severity error;
wait;
end process;

assert_1 : process
begin
wait until rising_edge(clk);
assert q = "0001" report "Error: q = " & to_string(q) severity error;
wait until rising_edge(clk);
assert q = "0010" report "Error: q = " & to_string(q) severity error;
wait until rising_edge(clk);
assert q = "0011" report "Error: q = " & to_string(q) severity error;
wait until rising_edge(clk);
assert q = "0100" report "Error: q = " & to_string(q) severity error;
wait until rising_edge(clk);
assert q = "0101" report "Error: q = " & to_string(q) severity error;
wait until rising_edge(clk);
assert q = "0110" report "Error: q = " & to_string(q) severity error;
wait until rising_edge(clk);
assert q = "0111" report "Error: q = " & to_string(q) severity error;
wait until rising_edge(clk);
assert q = "1000" report "Error: q = " & to_string(q) severity error;
wait until rising_edge(clk);
assert q = "1001" report "Error: q = " & to_string(q) severity error;
wait until rising_edge(clk);
assert q = "0000" report "Error: q = " & to_string(q) severity error;
wait;
end process;
end behavior;