2位数码管动态显示0-99,5个按键控制,功能分别是加一,减一,加二,减二,清零,用Verilog代码实现,共阳数码管

以下是Verilog代码实现：

module digital_display(clk, rst, add_one, sub_one, add_two, sub_two, clear, anode, cathode);

input clk, rst, add_one, sub_one, add_two, sub_two, clear;
output [6:0] anode;
output [9:0] cathode;

reg [9:0] count; // 计数器，从0-99

// 数码管对应的十进制数
parameter [9:0] digits [10] = {10'b00111111, // 0
                                10'b00000110, // 1
                                10'b01011011, // 2
                                10'b01001111, // 3
                                10'b01100110, // 4
                                10'b01101101, // 5
                                10'b01111101, // 6
                                10'b00000111, // 7
                                10'b01111111, // 8
                                10'b01101111}; // 9

// 当前显示的数
reg [3:0] digit1;
reg [3:0] digit2;

// 选择要显示的数码管
reg [1:0] select;

always @ (posedge clk or posedge rst) begin
    if (rst) begin
        count <= 0;
        digit1 <= 0;
        digit2 <= 0;
        select <= 0;
    end else begin
        if (clear) begin
            count <= 0;
            digit1 <= 0;
            digit2 <= 0;
            select <= 0;
        end else if (add_one) begin
            count <= (count == 99) ? 0 : count + 1;
        end else if (sub_one) begin
            count <= (count == 0) ? 99 : count - 1;
        end else if (add_two) begin
            count <= (count > 97) ? count + 2 - 100 : count + 2;
        end else if (sub_two) begin
            count <= (count < 2) ? count - 2 + 100 : count - 2;
        end
    end
end

// 显示数码管
always @ (posedge clk) begin
    if (select == 0) begin
        digit1 <= count % 10;
    end else if (select == 1) begin
        digit2 <= count / 10;
    end
    
    select <= (select == 1) ? 0 : 1;
    
    anode <= 7'b111_1110; // 共阳数码管，需要将anode置为0才能显示
    cathode <= digits[digit1];
    cathode[7] <= (select == 0) ? 1 : 0; // 指定哪个数码管显示
    
    #50;
    
    anode <= 7'b111_1101;
    cathode <= digits[digit2];
    cathode[7] <= (select == 1) ? 1 : 0;
    
    #50;
end

endmodule