基于quartus ii9.1软件的数字钟在六位数码管上动态显示verilog代码

以下是基于Quartus II 9.1软件的数字钟在六位数码管上动态显示的Verilog代码：

module clock(
input clk,
input rst,
output reg [5:0] seg1,
output reg [5:0] seg2,
output reg [5:0] seg3,
output reg [5:0] seg4,
output reg [5:0] seg5,
output reg [5:0] seg6
);

reg [3:0] sec; // seconds
reg [3:0] min; // minutes
reg [3:0] hr; // hours

// clock divider
reg [15:0] cnt;
parameter DIVIDER = 50000;

// BCD to 7-segment decoder
always @*
begin
case(sec[3:0])
4'd0: seg1 = 6'b000000;
4'd1: seg1 = 6'b000001;
4'd2: seg1 = 6'b000010;
4'd3: seg1 = 6'b000011;
4'd4: seg1 = 6'b000100;
4'd5: seg1 = 6'b000101;
4'd6: seg1 = 6'b000110;
4'd7: seg1 = 6'b000111;
4'd8: seg1 = 6'b001000;
4'd9: seg1 = 6'b001001;
default: seg1 = 6'b111111;
endcase

case(min[3:0])
4'd0: seg2 = 6'b000000;
4'd1: seg2 = 6'b000001;
4'd2: seg2 = 6'b000010;
4'd3: seg2 = 6'b000011;
4'd4: seg2 = 6'b000100;
4'd5: seg2 = 6'b000101;
4'd6: seg2 = 6'b000110;
4'd7: seg2 = 6'b000111;
4'd8: seg2 = 6'b001000;
4'd9: seg2 = 6'b001001;
default: seg2 = 6'b111111;
endcase

case(hr[3:0])
4'd0: seg3 = 6'b000000;
4'd1: seg3 = 6'b000001;
4'd2: seg3 = 6'b000010;
4'd3: seg3 = 6'b000011;
4'd4: seg3 = 6'b000100;
4'd5: seg3 = 6'b000101;
4'd6: seg3 = 6'b000110;
4'd7: seg3 = 6'b000111;
4'd8: seg3 = 6'b001000;
4'd9: seg3 = 6'b001001;
default: seg3 = 6'b111111;
endcase
end

// clock counter
always @(posedge clk)
begin
if (rst) begin
cnt <= 0;
sec <= 0;
min <= 0;
hr <= 0;
end
else begin
cnt <= cnt + 1;

if (cnt >= DIVIDER) begin
cnt <= 0;
sec <= sec + 1;

if (sec >= 60) begin
sec <= 0;
min <= min + 1;

if (min >= 60) begin
min <= 0;
hr <= hr + 1;

if (hr >= 24) begin
hr <= 0;
end
end
end
end
end
end

endmodule

在这个Verilog代码中，我们定义了一个数字钟模块，包括6个6位数码管的输出和一个时钟和复位输入。我们还定义了3个寄存器，分别用于存储秒、分钟和小时。我们使用一个计数器来计算时钟周期，并将其用于分频器，以便每秒更新一次计数器。在时钟计数器模块中，我们通过检查秒、分钟和小时的值来将它们转换为6位数码管的输出。