UART串口通信verilog代码设计

以下是一个简单的 UART 串口通信的 verilog 代码设计：

module uart(
    input clk,
    input reset_n,
    input rx,
    output tx,
    output reg [7:0] data_out,
    input [7:0] data_in,
    output reg tx_busy
);

// 定义常量
parameter BAUD_RATE = 9600;
parameter CLOCK_FREQ = 50000000;

// 定义寄存器
reg [2:0] state;
reg [3:0] bit_count;
reg [15:0] baud_divider;
reg [7:0] shift_reg;
reg [7:0] tx_data;

// 定义状态常量
parameter IDLE = 3'd0;
parameter START_BIT = 3'd1;
parameter DATA_BITS = 3'd2;
parameter STOP_BIT = 3'd3;

// 初始化
initial begin
    state <= IDLE;
    tx_busy <= 0;
    bit_count <= 0;
    baud_divider <= CLOCK_FREQ / BAUD_RATE;
end

// 接收器状态机
always @(posedge clk or negedge reset_n) begin
    if (~reset_n) begin
        state <= IDLE;
        data_out <= 8'h00;
        bit_count <= 0;
        shift_reg <= 8'h00;
    end else begin
        case (state)
            IDLE: begin
                if (~rx) begin
                    state <= START_BIT;
                    bit_count <= 0;
                    shift_reg <= 8'h00;
                end
            end
            START_BIT: begin
                if (bit_count < 8) begin
                    shift_reg[bit_count] <= rx;
                    bit_count <= bit_count + 1;
                end else begin
                    state <= DATA_BITS;
                    bit_count <= 0;
                    data_out <= shift_reg;
                end
            end
            DATA_BITS: begin
                if (bit_count < 8) begin
                    shift_reg[bit_count] <= rx;
                    bit_count <= bit_count + 1;
                end else begin
                    state <= STOP_BIT;
                    bit_count <= 0;
                end
            end
            STOP_BIT: begin
                if (~rx) begin
                    state <= START_BIT;
                    bit_count <= 0;
                    shift_reg <= 8'h00;
                end else begin
                    state <= IDLE;
                    bit_count <= 0;
                    shift_reg <= 8'h00;
                end
            end
            default: state <= IDLE;
        endcase
    end
end

// 发送器状态机
always @(posedge clk or negedge reset_n) begin
    if (~reset_n) begin
        state <= IDLE;
        tx_busy <= 0;
        bit_count <= 0;
        shift_reg <= 8'h00;
        tx_data <= 8'h00;
    end else begin
        case (state)
            IDLE: begin
                if (tx_busy) begin
                    state <= START_BIT;
                    bit_count <= 0;
                    shift_reg <= 8'h00;
                end else if (data_in != 8'h00) begin
                    state <= START_BIT;
                    bit_count <= 0;
                    shift_reg <= 8'h00;
                    tx_data <= data_in;
                    tx_busy <= 1;
                end
            end
            START_BIT: begin
                if (bit_count < 8) begin
                    shift_reg[bit_count] <= tx_data[bit_count];
                    bit_count <= bit_count + 1;
                end else begin
                    state <= DATA_BITS;
                    bit_count <= 0;
                    tx <= 0;
                end
            end
            DATA_BITS: begin
                if (bit_count < 8) begin
                    shift_reg[bit_count] <= tx_data[bit_count];
                    bit_count <= bit_count + 1;
                end else begin
                    state <= STOP_BIT;
                    bit_count <= 0;
                    tx <= 1;
                end
            end
            STOP_BIT: begin
                if (bit_count < 1) begin
                    shift_reg[0] <= 1;
                    bit_count <= bit_count + 1;
                end else begin
                    state <= IDLE;
                    bit_count <= 0;
                    shift_reg <= 8'h00;
                    tx_data <= 8'h00;
                    tx_busy <= 0;
                end
            end
            default: state <= IDLE;
        endcase
    end
end

endmodule

该代码实现了一个简单的异步串口通信，支持接收和发送 8 位数据。具体可以根据实际需求进行修改和扩展。