写一个verilog状态机

module fsm(
input clk, //时钟信号
input rst, //复位信号
input start, //开始信号
input stop, //停止信号
output reg led //LED输出信号
);

//定义状态枚举类型
typedef enum logic [1:0] {
IDLE_STATE, //空闲状态
START_STATE, //开始状态
STOP_STATE //停止状态
} STATE;

//定义状态变量和计数器
reg [1:0] current_state, next_state;
reg [7:0] count;

//状态转移逻辑
always @ (posedge clk, posedge rst) begin
if (rst) begin
current_state <= IDLE_STATE;
count <= 0;
end
else begin
current_state <= next_state;
if (current_state == STOP_STATE) begin
count <= 0;
end
else if (start) begin
count <= count + 1;
end
end
end

//状态控制逻辑
always @ (current_state, count) begin
case (current_state)
IDLE_STATE: begin
if (start) begin
next_state = START_STATE;
end
else begin
next_state = IDLE_STATE;
end
led = 0;
end
START_STATE: begin
if (count >= 10) begin
next_state = STOP_STATE;
end
else if (stop) begin
next_state = IDLE_STATE;
end
else begin
next_state = START_STATE;
end
led = 1;
end
STOP_STATE: begin
next_state = IDLE_STATE;
led = 0;
end
endcase
end

endmodule