使用Verilog设计一个状态机模拟交通灯。该状态机应完成如下功能： （1）红黄绿三色灯，高电平时点亮。 （2）南北路口：红灯亮50s ->黄灯亮3s ->绿灯亮40s-> （3）FPGA所接晶振频率为50MHz。

module traffic_light(
input clk,
output reg red,
output reg yellow,
output reg green
);

parameter red_time = 50_000_000; // 50s
parameter yellow_time = 3_000_000; // 3s
parameter green_time = 40_000_000; // 40s

reg [31:0] counter;
reg [1:0] state;

always @(posedge clk) begin
case(state)
2'b00: begin // Red light
red <= 1;
yellow <= 0;
green <= 0;
if(counter == red_time) begin
counter <= 0;
state <= 2'b01;
end else begin
counter <= counter + 1;
end
end
2'b01: begin // Yellow light
red <= 0;
yellow <= 1;
green <= 0;
if(counter == yellow_time) begin
counter <= 0;
state <= 2'b10;
end else begin
counter <= counter + 1;
end
end
2'b10: begin // Green light
red <= 0;
yellow <= 0;
green <= 1;
if(counter == green_time) begin
counter <= 0;
state <= 2'b00;
end else begin
counter <= counter + 1;
end
end
endcase
end

endmodule