Consider two 4-bit binary numbers A and B. Bits of A are a3, a2, a1, and a0, and bits of B are b3, b2, b1, and b0. A is greater than B if a3 is 1 and b3 is 0, but if a3 and b3 are the same, then if a2 is 1 and b2 is 0, we can determine that A is greater than B. This evaluation continues until a0 and b0 are considered. If a0 and b0 are equal then A and B are equal. Using discrete gates and Verilog gate primitives build a 4-bit comparator that generates a 1 on its GT output when its 4-bit input A is greater than its B input, and a 1 on its EQ output when A and B are equal. Use the generate statement and other Verilog iterative logic support structures.用中文回答

这道题要求我们使用离散门和Verilog门原语来构建一个4位比较器，当A大于B时，在GT输出上生成1，在A和B相等时，在EQ输出上生成1。比较过程从a3和b3开始，如果a3是1且b3是0，则认为A大于B。如果a3和b3相同，则继续比较a2和b2。此评估继续直到考虑a0和b0。如果a0和b0相等，则A和B相等。我们可以使用generate语句和其他Verilog迭代逻辑支持结构来实现这个4位比较器。