uvm中finish_item源码
时间: 2023-11-27 11:54:21 浏览: 29
以下是 UVM 中 `finish_item` 函数的简化源码:
```systemverilog
virtual function void finish_item(uvm_sequence_item item, uvm_sequence_base parent = null);
if(parent == null) parent = get_parent();
if(parent != null)
parent.item_done(item);
else
`uvm_error("UVM/SEQ/NULL_PARENT", $sformatf("Sequence item %0d has a null parent.", item.get_transaction_id()))
endfunction
```
这个函数的作用是告诉父序列,当前的项已经完成执行了。如果没有父序列,将会输出一个错误信息。
相关问题
uvm中start_item的源码
`start_item`函数是UVM中序列化对象的一种机制,用于将序列化对象插入到序列执行队列中。以下是UVM中`start_item`的源代码:
```systemverilog
function bit uvm_sequence_base::start_item (uvm_sequence_item item,
uvm_sequencer_base sequencer,
bit set_priority = 0,
string source_file = "",
int source_line = 0);
uvm_sequence_item item_copy;
uvm_tlm_transaction_base t;
uvm_component comp = get_parent();
uvm_phase phase;
if (!item)
`uvm_fatal("NOITEM","Attempting to start a NULL sequence_item")
if (!sequencer)
`uvm_fatal("NOSEQ","Attempting to start a sequence_item with a NULL sequencer")
if (comp is uvm_root) begin
`uvm_warning("SEQROOT",{"Attempt to start sequence '",get_type_name(),
"' outside of a phase process. Ignored."})
return 0;
end
// Create a copy of the item
if(item.try_clone(item_copy) == 0) begin
`uvm_error("CLONE", {"Unable to clone sequence item '",item.get_type_name(),"'"})
return 0;
end
// Check for TLM analysis ports
if(item_copy.get_type_name() == "uvm_tlm_analysis_port_base") begin
t = item_copy;
t.set_source_info(source_file, source_line);
t.analysis_imp.connect(item_copy.analysis_export);
t.write(t);
return 1;
end
// Set the item's sequencer
item_copy.set_sequencer(sequencer);
// Set the item's source info
item_copy.set_source_info(source_file, source_line);
// Set the item's priority
if (set_priority)
item_copy.set_priority(m_priority);
// If in a run phase, start the item
phase = comp.get_phase();
if (phase != null && phase.get_name() == "run") begin
if (!sequencer.start_item(item_copy)) begin
`uvm_error("NOSEQITEM", {"Failed to start sequence item ",
item_copy.get_type_name()," with sequencer ",
sequencer.get_type_name()})
return 0;
end
end
else
m_req_q.push_back(item_copy);
return 1;
endfunction
```
此函数接收四个参数:
- `item`:要插入序列执行队列中的序列化对象。
- `sequencer`:将序列化对象插入到其执行队列中的UVM序列器。
- `set_priority`:指示是否应将`item`的优先级设置为该序列的优先级。
- `source_file`和`source_line`:指示从哪个源代码文件和行开始创建序列化对象。
该函数首先检查传递的参数是否有效。然后,它会复制序列化对象并将其设置在传递的`sequencer`中。如果序列化对象是一个TLM分析端口,则该函数会将其连接到分析导出,并通过`write`函数写入分析对象。如果在运行阶段,则该函数将使用传递的`sequencer`启动序列化对象。否则,它将序列化对象插入到要求队列中。函数返回1表示成功,返回0表示失败。
uvm_seq_item_pull_port
uvm_seq_item_pull_port是UVM中的一个TLM端口,用于在Driver和Sequencer之间进行通信。它派生自uvm_seq_item_pull_export和uvm_seq_item_pull_imp,并定义了参数类型REQ和RSP。\[2\]通过seq_item_port的方法,Driver可以从Sequencer获取请求项,并将响应项发送回Sequencer。在Sequence中,可以使用get_response()方法来获取返回的item。\[3\]因此,uvm_seq_item_pull_port在UVM中起到了连接Driver和Sequencer的作用。\[1\]
#### 引用[.reference_title]
- *1* *3* [UVM: Driver和Sequencer之间的握手机制(二)](https://blog.csdn.net/weixin_43249032/article/details/83994995)[target="_blank" data-report-click={"spm":"1018.2226.3001.9630","extra":{"utm_source":"vip_chatgpt_common_search_pc_result","utm_medium":"distribute.pc_search_result.none-task-cask-2~all~insert_cask~default-1-null.142^v91^insertT0,239^v3^insert_chatgpt"}} ] [.reference_item]
- *2* [UVM-- Sequencer和driver](https://blog.csdn.net/weixin_45680021/article/details/124437797)[target="_blank" data-report-click={"spm":"1018.2226.3001.9630","extra":{"utm_source":"vip_chatgpt_common_search_pc_result","utm_medium":"distribute.pc_search_result.none-task-cask-2~all~insert_cask~default-1-null.142^v91^insertT0,239^v3^insert_chatgpt"}} ] [.reference_item]
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