用quartus2实现msk调制解调的VHDL完整代码

以下是一个简单的MSK调制解调器的VHDL代码示例，使用Quartus II软件实现。该代码通过使用带有相位差分解调器的Costas环路来实现解调。该代码仅供参考。

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity MSK_ModDemod is
    Port ( Mod_Clk : in STD_LOGIC;
           Demod_Clk : in STD_LOGIC;
           Carrier_Freq : in STD_LOGIC_VECTOR (15 downto 0);
           Bit_Rate : in STD_LOGIC_VECTOR (15 downto 0);
           Mod_Data : in STD_LOGIC_VECTOR (7 downto 0);
           Demod_Data : out STD_LOGIC_VECTOR (7 downto 0));
end MSK_ModDemod;

architecture Behavioral of MSK_ModDemod is

    signal mod_clk_div : std_logic_vector(7 downto 0);
    signal demod_clk_div : std_logic_vector(7 downto 0);
    signal mod_data_i : std_logic_vector(7 downto 0);
    signal mod_data_q : std_logic_vector(7 downto 0);
    signal modulated_signal : std_logic_vector(1023 downto 0);
    signal demodulated_signal : std_logic_vector(1023 downto 0);
    signal modulated_signal_i : std_logic_vector(1023 downto 0);
    signal modulated_signal_q : std_logic_vector(1023 downto 0);
    signal modulated_signal2_i : std_logic_vector(1023 downto 0);
    signal modulated_signal2_q : std_logic_vector(1023 downto 0);
    signal costas_error : std_logic_vector(1023 downto 0);
    signal costas_out_i : std_logic_vector(1023 downto 0);
    signal costas_out_q : std_logic_vector(1023 downto 0);
    signal demod_data : std_logic_vector(7 downto 0);
    
    constant pi : real := 3.14159265358979323846;
    constant fs : real := 1.0e6;
    constant fc : real := 10.0e6;
    constant T : real := 1.0/fs;
    constant Ts : real := 1.0/Bit_Rate'val;
    constant A : real := 1.0;
    constant alpha : real := 0.5*pi*Bit_Rate'val/fs;
    constant beta : real := 0.5*pi*Carrier_Freq'val/fs;
    constant gamma : real := 0.5*pi*(Carrier_Freq'val-Bit_Rate'val)/fs;
    
    component Costas_Loop is
        Port ( Clk : in STD_LOGIC;
               Input_I : in STD_LOGIC_VECTOR(7 downto 0);
               Input_Q : in STD_LOGIC_VECTOR(7 downto 0);
               Output_I : out STD_LOGIC_VECTOR(7 downto 0);
               Output_Q : out STD_LOGIC_VECTOR(7 downto 0);
               Error : out STD_LOGIC_VECTOR(7 downto 0));
    end component;
    
begin

    mod_clk_div <= std_logic_vector(unsigned(Carrier_Freq)*T*2**8);
    demod_clk_div <= std_logic_vector(unsigned(Carrier_Freq+Bit_Rate)*T*2**8);
    
    process(Mod_Clk)
    begin
        if rising_edge(Mod_Clk) then
            mod_data_i <= Mod_Data;
            mod_data_q <= not Mod_Data;
            
            for i in 0 to 1023 loop
                if i*T*fs < Ts then
                    modulated_signal_i(i) <= mod_data_i(0);
                    modulated_signal_q(i) <= mod_data_q(0);
                elsif (i*T*fs >= Ts) and (i*T*fs < 2*Ts) then
                    modulated_signal_i(i) <= mod_data_i(1);
                    modulated_signal_q(i) <= mod_data_q(1);
                elsif (i*T*fs >= 2*Ts) and (i*T*fs < 3*Ts) then
                    modulated_signal_i(i) <= mod_data_i(2);
                    modulated_signal_q(i) <= mod_data_q(2);
                elsif (i*T*fs >= 3*Ts) and (i*T*fs < 4*Ts) then
                    modulated_signal_i(i) <= mod_data_i(3);
                    modulated_signal_q(i) <= mod_data_q(3);
                elsif (i*T*fs >= 4*Ts) and (i*T*fs < 5*Ts) then
                    modulated_signal_i(i) <= mod_data_i(4);
                    modulated_signal_q(i) <= mod_data_q(4);
                elsif (i*T*fs >= 5*Ts) and (i*T*fs < 6*Ts) then
                    modulated_signal_i(i) <= mod_data_i(5);
                    modulated_signal_q(i) <= mod_data_q(5);
                elsif (i*T*fs >= 6*Ts) and (i*T*fs < 7*Ts) then
                    modulated_signal_i(i) <= mod_data_i(6);
                    modulated_signal_q(i) <= mod_data_q(6);
                else
                    modulated_signal_i(i) <= mod_data_i(7);
                    modulated_signal_q(i) <= mod_data_q(7);
                end if;
            end loop;
            
            for i in 0 to 1023 loop
                modulated_signal2_i(i) <= modulated_signal_i(i)*cos(i*T*fs*2.0*pi*Carrier_Freq'val);
                modulated_signal2_q(i) <= modulated_signal_q(i)*sin(i*T*fs*2.0*pi*Carrier_Freq'val);
            end loop;
            
            modulated_signal <= modulated_signal2_i + modulated_signal2_q;
        end if;
    end process;
    
    process(Demod_Clk)
    begin
        if rising_edge(Demod_Clk) then
            
            for i in 0 to 1023 loop
                costas_error(i) <= costas_error(i) + (modulated_signal_i(i)*costas_out_q(i) - costas_out_i(i)*modulated_signal_q(i));
                costas_out_i(i) <= modulated_signal_i(i)*cos(i*T*fs*2.0*pi*Carrier_Freq'val + costas_error(i)*beta);
                costas_out_q(i) <= modulated_signal_q(i)*sin(i*T*fs*2.0*pi*Carrier_Freq'val + costas_error(i)*beta);
            end loop;
            
            for i in 1 to 1023 loop
                if costas_out_i(i-1) < 0 and costas_out_i(i) >= 0 then
                    demod_data <= demod_data(6 downto 0) & costas_out_q(i-1);
                end if;
            end loop;
            
            Demod_Data <= demod_data;
        end if;
    end process;
    
    Costas : Costas_Loop port map(Demod_Clk, costas_out_i, costas_out_q, costas_out_i, costas_out_q, costas_error);

end Behavioral;