用verilog写无符号数和有符号数乘法器及测试语句
时间: 2024-02-02 14:03:50 浏览: 25
无符号数乘法器:
```
module unsigned_multiplier(
input [31:0] a,
input [31:0] b,
output reg [63:0] result
);
always @(*) begin
result = a * b;
end
endmodule
```
有符号数乘法器:
```
module signed_multiplier(
input signed [31:0] a,
input signed [31:0] b,
output reg signed [63:0] result
);
always @(*) begin
result = a * b;
end
endmodule
```
测试语句:
```
module test_multiplier;
reg [31:0] a, b;
wire [63:0] unsigned_result;
wire signed [63:0] signed_result;
unsigned_multiplier UM(a, b, unsigned_result);
signed_multiplier SM(a, b, signed_result);
initial begin
a = 10;
b = 20;
#10;
$display("Unsigned result: %d", unsigned_result);
$display("Signed result: %d", signed_result);
#10;
a = 2147483647;
b = 1;
#10;
$display("Unsigned result: %d", unsigned_result);
$display("Signed result: %d", signed_result);
#10;
a = -2147483647;
b = -1;
#10;
$display("Unsigned result: %d", unsigned_result);
$display("Signed result: %d", signed_result);
#10;
a = -2147483647;
b = 2147483647;
#10;
$display("Unsigned result: %d", unsigned_result);
$display("Signed result: %d", signed_result);
end
endmodule
```
这个测试语句测试了四种情况:
1. 两个正整数相乘
2. 一个正整数和1相乘,测试是否会溢出
3. 两个负整数相乘,测试是否会溢出
4. 一个正整数和一个负整数相乘,测试是否会溢出