Consider two 4-bit binary numbers A and B. Bits of A are a3, a2, a1, and a0, and bits of B are b3, b2, b1, and b0. A is greater than B if a3 is 1 and b3 is 0, but if a3 and b3 are the same, then if a2 is 1 and b2 is 0, we can determine that A is greater than B. This evaluation continues until a0 and b0 are considered. If a0 and b0 are equal then A and B are equal. Using discrete gates and Verilog gate primitives build a 4-bit comparator that generates a 1 on its GT output when its 4-bit input A is greater than its B input, and a 1 on its EQ output when A and B are equal. Use the generate statement and other Verilog iterative logic support structures.

Here's one possible implementation using Verilog:

module comparator(A, B, GT, EQ);
  parameter WIDTH = 4;
  input [WIDTH-1:0] A, B;
  output GT, EQ;

  wire [WIDTH:0] greater;
  wire [WIDTH:0] equal;

  assign greater[0] = 1'b0;
  assign equal[0] = 1'b1;

  genvar i;
  generate
    for (i = 0; i < WIDTH; i = i + 1) begin : COMPARE
      assign greater[i+1] = (A[i] > B[i]) ? 1'b1 :
                            (A[i] < B[i]) ? 1'b0 :
                            greater[i];
      assign equal[i+1]   = (A[i] == B[i]) ? equal[i] : 1'b0;
    end
  endgenerate

  assign GT = greater[WIDTH];
  assign EQ = equal[WIDTH];

endmodule

This module takes in two 4-bit binary inputs A and B, and outputs a 1 on GT if A is greater than B, and a 1 on EQ if A and B are equal. It uses a generate loop to compare each bit of A and B in turn, building up the greater and equal wires as it goes. At the end, GT is set to the last bit of greater, and EQ is set to the last bit of equal.

The comparator uses the ?: ternary operator to select either 1'b1 or 1'b0 based on whether A[i] is greater than, less than, or equal to B[i]. If A[i] is greater than B[i], then greater[i+1] is set to 1'b1. If A[i] is less than B[i], then greater[i+1] is set to 1'b0. If A[i] is equal to B[i], then greater[i+1] is set to the value of greater[i], which represents the comparison of the previous bits.

Note that this implementation assumes that A and B are valid binary inputs, meaning that they consist only of 0's and 1's. If A or B are invalid, then the behavior of the comparator is undefined.