module test; typedef struct packed { logic [9:-1][2:0] a; //REQ-EXT-10001, REQ-EXT-10004 } ST1; typedef struct { ST1 st1; logic [2:0] b; } ST2; typedef struct { logic [31:0] c; // ST3 definition missing } ST3; typedef struct { ST3 st3; ST2 st2_arr[3:0]; } ST4; initial begin ST2 st2; ST2 st2_1 = {3'b101, {ST1{10'b110}}, {ST1{20'b10101010101010}},{ST1{30'b1}}}; ST2 st2_2 = {3'b010, {ST1{10'b101}}, {ST1{20'b01010101010101}},{ST1{30'b0}}}; st2 = {3'b1, {ST1{10'b110}}, {ST1{20'b10101010101010}}, {ST1{30'b1}}}; $display("%p",st2); //CHECK-001:'{a:'h1}, st2:'{'a:'h1}, '{a:'h0},'{a:h1}}} $display("st2_1:%p", st2_1); //CHECK-002 $display("st2_2:%p", st2_2); //CHECK-003 end endmodule when compiled by vcs, it says following verilog source has syntax error: "sc_assignment_pattern_035.sv", 35:token is '{' ST2 st2_1={3'b101, {ST1{10'b110}},{ST1{20'b1010101010}},{ST1{30'b1}}}; how to fix this syntax error so that it can be compiled by vcs?

The syntax error in the verilog source is due to the use of the packed struct initialization syntax '{ST1{}}' inside another struct initialization. To fix this, we can use the 'repeat' operator to initialize the packed struct arrays as follows:

ST2 st2_1 = {3'b101, {}}; 
repeat (3) begin 
    st2_1.st1.a[2*(i+1)-1:2*i] = 10'b110; 
end 
repeat (5) begin 
    st2_1.st1.a[2*(i+4)+2:2*(i+4)-1] = 10'b1010; 
end 
repeat (10) begin 
    st2_1.st1.a[2*(i+9)+2:2*(i+9)-1] = 10'b101010; 
end 
st2_1.st1.a[31:30] = 2'b01; 

Similarly, we can initialize the other struct 'st2_2' using the 'repeat' operator.