module seg( input wire clk , //100MHz input wire rst_n , //low valid input wire [17:0] data_in , //待显示数据 output reg [6:0] hex1 , // -共阳极，低电平有效 output reg [6:0] hex2 , // - output reg [6:0] hex3 , // - output reg [6:0] hex4 //熄灭 ); //parameter define localparam NUM_0 = 8'b1100_0000, NUM_1 = 8'b1111_1001, NUM_2 = 8'b1010_0100, NUM_3 = 8'b1011_0000, NUM_4 = 8'b1001_1001, NUM_5 = 8'b1001_0010, NUM_6 = 8'b1000_0010, NUM_7 = 8'b1111_1000, NUM_8 = 8'b1000_0000, NUM_9 = 8'b1001_0000, NUM_A = 8'b1000_1000, NUM_B = 8'b1000_0011, NUM_C = 8'b1100_0110, NUM_D = 8'b1010_0001, NUM_E = 8'b1000_0110, NUM_F = 8'b1000_1110, ALL_LIGHT = 8'b0000_0000, LIT_OUT = 8'b1111_1111; //reg 、wire define reg [3:0] cm_hund ;//100cm reg [3:0] cm_ten ;//10cm reg [3:0] cm_unit ;//1cm always @(posedge clk or negedge rst_n)begin if(!rst_n)begin cm_hund <= 'd0; cm_ten <= 'd0; cm_unit <= 'd0; end else begin cm_hund <= data_in / 10 ** 2; cm_ten <= data_in / 10**1 % 10; cm_unit <= data_in/10**0 % 10; end end always @(posedge clk or negedge rst_n)begin if(!rst_n)begin hex1 <= ALL_LIGHT; hex2 <= ALL_LIGHT; hex3 <= ALL_LIGHT; hex4 <= ALL_LIGHT; end else begin hex1 <= hex_data(cm_unit); hex2 <= hex_data(cm_ten); hex3 <= hex_data(cm_hund); hex4 <= LIT_OUT; end end //always end function [6:0] hex_data; //函数不含时序逻辑相关 input [03:00] data_i;//至少一个输入 begin case(data_i) 'd0:hex_data = NUM_0; 'd1:hex_data = NUM_1; 'd2:hex_data = NUM_2; 'd3:hex_data = NUM_3; 'd4:hex_data = NUM_4; 'd5:hex_data = NUM_5; 'd6:hex_data = NUM_6; 'd7:hex_data = NUM_7; 'd8:hex_data = NUM_8; 'd9:hex_data = NUM_9; default:hex_data = ALL_LIGHT; endcase end endfunction endmodule

这是一个Verilog HDL写的模块，可以实现数字显示器的功能。其中，模块的输入包括时钟信号clk、复位信号rst_n和待显示的数据data_in，输出包括4个七段数码管的控制信号hex1、hex2、hex3和hex4。模块中使用了parameter定义常量和reg、wire定义寄存器和线网，同时使用了always块和function函数实现时序逻辑和数字转换功能。具体实现是将待显示的数据转换为3个数字，然后通过函数将数字转换为对应的七段数码管控制信号。