verilog电子钟数码管

下面是一个简单的Verilog代码实现数码管电子钟：

module clock(
    input clk,
    output reg [3:0] segA,
    output reg [3:0] segB,
    output reg [3:0] segC,
    output reg [3:0] segD
    );

//时针分针秒针计数器
reg [5:0] sec_cnt = 0;
reg [5:0] min_cnt = 0;
reg [4:0] hr_cnt = 0;

//时针分针秒针寄存器
reg [3:0] sec_reg = 0;
reg [3:0] min_reg = 0;
reg [3:0] hr_reg = 0;

//数码管显示寄存器
reg [7:0] seg_reg = 0;

//数码管扫描控制信号
reg [1:0] scan_cnt = 0;

//时钟分频计数器
reg [9:0] clk_div = 0;

//时针分针秒针计数器递增
always @(posedge clk) begin
    if (sec_cnt == 59) begin
        sec_cnt <= 0;
        if (min_cnt == 59) begin
            min_cnt <= 0;
            if (hr_cnt == 23) begin
                hr_cnt <= 0;
            end else begin
                hr_cnt <= hr_cnt + 1;
            end
        end else begin
            min_cnt <= min_cnt + 1;
        end
    end else begin
        sec_cnt <= sec_cnt + 1;
    end
end

//时针分针秒针寄存器更新
always @(posedge clk) begin
    sec_reg <= sec_cnt;
    min_reg <= min_cnt;
    hr_reg <= hr_cnt;
end

//数码管显示寄存器更新
always @(posedge clk) begin
    case(scan_cnt)
        2'b00: seg_reg <= {4'b0000, hr_reg[3:0]};
        2'b01: seg_reg <= {4'b0000, min_reg[3:0]};
        2'b10: seg_reg <= {4'b0000, sec_reg[3:0]};
        2'b11: seg_reg <= 8'b11111111;
    endcase
end

//数码管扫描控制信号递增
always @(posedge clk) begin
    if (scan_cnt == 2'b10) begin
        scan_cnt <= 2'b00;
    end else begin
        scan_cnt <= scan_cnt + 1;
    end
end

//数码管显示
always @(*) begin
    case(seg_reg)
        8'b00000001: begin segA = 4'b0001; segB = 4'b0000; segC = 4'b0000; segD = 4'b0000; end // 0
        8'b10011110: begin segA = 4'b0000; segB = 4'b0001; segC = 4'b0000; segD = 4'b0000; end // 1
        8'b00100101: begin segA = 4'b0000; segB = 4'b0000; segC = 4'b0001; segD = 4'b0000; end // 2
        8'b00001101: begin segA = 4'b0000; segB = 4'b0000; segC = 4'b0010; segD = 4'b0000; end // 3
        8'b10011000: begin segA = 4'b0000; segB = 4'b0000; segC = 4'b0000; segD = 4'b0001; end // 4
        8'b01001000: begin segA = 4'b0000; segB = 4'b0010; segC = 4'b0000; segD = 4'b0000; end // 5
        8'b01000000: begin segA = 4'b0001; segB = 4'b0000; segC = 4'b0000; segD = 4'b0000; end // 6
        8'b00011101: begin segA = 4'b0000; segB = 4'b0000; segC = 4'b0000; segD = 4'b0010; end // 7
        8'b00000000: begin segA = 4'b0000; segB = 4'b0000; segC = 4'b0000; segD = 4'b0000; end // 8
        8'b00011000: begin segA = 4'b0000; segB = 4'b0000; segC = 4'b0000; segD = 4'b0010; end // 9
        default: begin segA = 4'b0000; segB = 4'b0000; segC = 4'b0000; segD = 4'b0000; end
    endcase
end

//时钟分频
always @(posedge clk) begin
    if (clk_div == 1000) begin
        clk_div <= 0;
    end else begin
        clk_div <= clk_div + 1;
    end
end

endmodule

该代码实现了一个带有四个数码管的电子钟，使用时钟信号clk作为输入，以1kHz的频率进行时钟分频，实现秒针、分针、时针的计数，以及数码管的扫描和显示功能。需要注意的是，该代码中使用了常量8'b11111111代表数码管不显示，这是为了防止数码管扫描时出现闪烁。

此外，还需要使用数码管驱动芯片控制数码管的亮灭，这里不再赘述。