module test; typedef_packed struct { bit [9:-1][2:0] a; ///REQ-EXT-10001, REQ-EXT-10004 bit [3:0] b; } packed ST1; typedef_packed struct { ST1 st1; ST1 st2[3:0]; } ST2; logic clk; always @ (posedge clk) begin ST2 st2 = '{ {10{1'b1}}, '{3'b1, 3'b0, 12'hFFF,3'b1}}; $display("st2 before:%0d '%h", st2.st2[0].b, st2.st2[0].a); ST2 st3; end endmodule when compiled by vcs, it reports error: Parsing design file 'sc_assignment_pattern_058.sv' Error-[SE] Syntax Error Following verilog source has syntax error: "sc_assignment_pattern_058.sv", 30: token is 'st3' ST2 st3; how should I fix this error?

The error is caused by placing the declaration of `st3` inside the always block without any assignment. To fix the error, you can either remove the declaration of `st3` or add an assignment to it. For example, you can assign a value to `st3` to make the declaration valid:

module test;
    typedef_packed struct {
        bit [9:-1][2:0] a; ///REQ-EXT-10001, REQ-EXT-10004
        bit [3:0] b;
    } packed ST1;

    typedef_packed struct {
        ST1 st1;
        ST1 st2[3:0];
    } ST2;

    logic clk;

    always @ (posedge clk) begin
        ST2 st2 = '{ {10{1'b1}}, '{3'b1, 3'b0, 12'hFFF,3'b1}};
        $display("st2 before:%0d '%h", st2.st2[0].b, st2.st2[0].a);
        ST2 st3 = '{ '{ {9{1'b0}}, 4'h5, {{10{3'b0}}, 3'b1, 12'hABC, 3'b0}}};
    end
endmodule