RTL级描述四位数码管秒表

下面是一个简单的RTL级描述，用于控制四位数码管的秒表：

module stopwatch(clk, reset, start, stop, digit0, digit1, digit2, digit3);

input clk, reset, start, stop;
output reg [6:0] digit0, digit1, digit2, digit3;

reg [3:0] seconds = 0;
reg [27:0] counter = 0;
reg running = 0;

always @(posedge clk or posedge reset) begin
    if (reset) begin
        counter <= 0;
        seconds <= 0;
        running <= 0;
    end else begin
        if (start && !stop) running <= 1;
        if (stop) running <= 0;
        if (running) counter <= counter + 1;
        if (counter == 50000000) begin
            counter <= 0;
            seconds <= seconds + 1;
        end
    end
end

always @(posedge clk or posedge reset) begin
    if (reset) begin
        digit0 <= 7'b111_1110;
        digit1 <= 7'b111_1110;
        digit2 <= 7'b111_1110;
        digit3 <= 7'b111_1110;
    end else begin
        case (seconds)
            0: begin digit0 <= 7'b111_1110; digit1 <= 7'b111_1110; digit2 <= 7'b111_1110; digit3 <= 7'b111_1111; end
            1: begin digit0 <= 7'b000_0110; digit1 <= 7'b000_0000; digit2 <= 7'b000_0000; digit3 <= 7'b000_0000; end
            2: begin digit0 <= 7'b111_1010; digit1 <= 7'b111_1111; digit2 <= 7'b000_0000; digit3 <= 7'b111_1111; end
            3: begin digit0 <= 7'b111_1110; digit1 <= 7'b111_1111; digit2 <= 7'b000_0000; digit3 <= 7'b111_1111; end
            4: begin digit0 <= 7'b000_0110; digit1 <= 7'b111_1111; digit2 <= 7'b000_0000; digit3 <= 7'b000_1100; end
            5: begin digit0 <= 7'b111_1010; digit1 <= 7'b111_1110; digit2 <= 7'b000_0000; digit3 <= 7'b111_1111; end
            6: begin digit0 <= 7'b111_1110; digit1 <= 7'b111_1110; digit2 <= 7'b000_0000; digit3 <= 7'b111_1111; end
            7: begin digit0 <= 7'b000_0010; digit1 <= 7'b000_0000; digit2 <= 7'b000_0000; digit3 <= 7'b111_1111; end
            8: begin digit0 <= 7'b111_1110; digit1 <= 7'b111_1110; digit2 <= 7'b000_0000; digit3 <= 7'b111_1111; end
            9: begin digit0 <= 7'b111_1010; digit1 <= 7'b111_1110; digit2 <= 7'b000_0000; digit3 <= 7'b111_1111; end
            default: begin digit0 <= 7'b111_1110; digit1 <= 7'b111_1110; digit2 <= 7'b111_1110; digit3 <= 7'b111_1110; end
        endcase
    end
end

endmodule

该模块包含四个输入（时钟信号`clk`、异步复位信号`reset`、启动信号`start`和停止信号`stop`），以及四个输出（四个数码管显示的七段码）。基于时钟信号，该模块实现了一个简单的计时器功能。当启动信号被置为高电平时，计时器开始计数；当停止信号被置为高电平时，计时器暂停。每秒钟，计时器会增加1秒，并且数码管会显示相应的秒数。在计时器开始工作之前，需要将异步复位信号置为高电平，以确保计时器处于正确的初始状态。