基于 VHDL 语言的定时器的设计该定时器 的设计要求如下： (1) 该定时器可以设置 20 分钟、30 分钟共两种模式，通过按键 set 进行设定，按动 时从 20 分钟到 30 分钟两种模式间切换，当设定好后按 start 键开始计时； (2) 该定时器具有清零功能（reset），按动时计时器清零，计时结束； (3) 该定时器当计时完成时，会通过输出端 speak 输出信号驱动蜂鸣器提示时间到； (4) 时钟信号是由 1KHz 信号（clkin）经过分频产生的秒信号(clkout)； (5) 四位数码管静态显示，高位两位显示分，低位两位显示秒。 设计具体要求： （1）各模块采用文本方法编辑该定时器，语言采用 VHDL 语言,检查编辑并编译,仿真验 证。 （2）采用层次化文件设计该定时器，检查编辑并编译进行波形仿真，观察输出波形，请设计出VHDL代码

非常感谢您的提问，以下是基于VHDL语言的定时器设计的代码实现：

-- 时钟分频模块
library ieee;
use ieee.std_logic_1164.all;

entity clk_divider is
    port(
        clk_in : in std_logic;
        clk_out : out std_logic
    );
end clk_divider;

architecture arch of clk_divider is
    signal cnt : integer range 0 to 9999 := 0;
begin
    process(clk_in)
    begin
        if rising_edge(clk_in) then
            cnt <= cnt + 1;
            if cnt = 9999 then
                cnt <= 0;
                clk_out <= not clk_out;
            end if;
        end if;
    end process;
end arch;

-- 数码管显示模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity seven_seg_display is
    port(
        clk_in : in std_logic;
        clk_out : in std_logic;
        reset : in std_logic;
        time : in std_logic_vector(15 downto 0);
        dig_out : out std_logic_vector(3 downto 0);
        a : out std_logic;
        b : out std_logic;
        c : out std_logic;
        d : out std_logic;
        e : out std_logic;
        f : out std_logic;
        g : out std_logic
    );
end seven_seg_display;

architecture arch of seven_seg_display is
    signal cnt : integer range 0 to 4999 := 0;
    signal sec : integer range 0 to 59 := 0;
    signal min : integer range 0 to 59 := 0;
    signal mode : integer range 0 to 1 := 0;
    signal dig_sel : integer range 0 to 3 := 0;
    signal dig_val : std_logic_vector(6 downto 0);
    signal speak : std_logic := '0';
    
    -- 数码管显示码表
    type seg_table is array(0 to 15) of std_logic_vector(6 downto 0);
    constant table : seg_table := (
        "0000001", -- 0
        "1001111", -- 1
        "0010010", -- 2
        "0000110", -- 3
        "1001100", -- 4
        "0100100", -- 5
        "0100000", -- 6
        "0001111", -- 7
        "0000000", -- 8
        "0000100", -- 9
        "0001000", -- A
        "1100000", -- b
        "0110001", -- C
        "1000010", -- d
        "0110000", -- E
        "0111000"  -- F
    );
    
begin
    process(clk_in)
    begin
        if rising_edge(clk_in) then
            if reset = '1' then
                cnt <= 0;
                sec <= 0;
                min <= 0;
                mode <= 0;
                dig_sel <= 0;
                dig_val <= table(0);
                speak <= '0';
            else
                cnt <= cnt + 1;
                if cnt = 4999 then
                    cnt <= 0;
                    sec <= sec + 1;
                    if sec = 60 then
                        sec <= 0;
                        min <= min + 1;
                        if min = 60 then
                            min <= 0;
                        end if;
                    end if;
                end if;
            end if;
        end if;
    end process;
    
    process(clk_out, reset)
    begin
        if reset = '1' then
            dig_sel <= 0;
            dig_val <= table(0);
            speak <= '0';
        else
            if dig_sel = 0 then
                if mode = 0 then
                    dig_val <= table(to_integer(unsigned(std_logic_vector(resize(min, 4)))) & table(to_integer(unsigned(std_logic_vector(resize(sec, 4)))) & "0000000");
                else
                    dig_val <= table(to_integer(unsigned(std_logic_vector(resize(min+20, 4)))) & table(to_integer(unsigned(std_logic_vector(resize(sec, 4)))) & "0000000");
                end if;
            elsif dig_sel = 1 then
                if mode = 0 then
                    dig_val <= table(to_integer(unsigned(std_logic_vector(resize(min, 4)))) & table(to_integer(unsigned(std_logic_vector(resize(sec, 4)))) & "0000000");
                else
                    dig_val <= table(to_integer(unsigned(std_logic_vector(resize(min+30, 4)))) & table(to_integer(unsigned(std_logic_vector(resize(sec, 4)))) & "0000000");
                end if;
            elsif dig_sel = 2 then
                dig_val <= "0000000" & "0000000" & "0000001";
            else
                dig_val <= "0000000" & "0000000" & std_logic_vector(speak);
            end if;
            
            dig_sel <= dig_sel + 1;
            if dig_sel = 4 then
                dig_sel <= 0;
                if mode = 0 and sec = 0 and min = 20 then
                    speak <= '1';
                elsif mode = 1 and sec = 0 and min = 30 then
                    speak <= '1';
                else
                    speak <= '0';
                end if;
            end if;
        end if;
    end process;
    
    a <= dig_val(6);
    b <= dig_val(5);
    c <= dig_val(4);
    d <= dig_val(3);
    e <= dig_val(2);
    f <= dig_val(1);
    g <= dig_val(0);
    dig_out <= std_logic_vector(to_unsigned(dig_sel, 4));
end arch;

-- 定时器模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity timer is
    port(
        clk_in : in std_logic;
        reset : in std_logic;
        set : in std_logic;
        start : in std_logic;
        speak : out std_logic;
        dig_out : out std_logic_vector(3 downto 0);
        a : out std_logic;
        b : out std_logic;
        c : out std_logic;
        d : out std_logic;
        e : out std_logic;
        f : out std_logic;
        g : out std_logic
    );