用VHDL设计一个下降沿触发、同步清零的十二进制计数器仿真代码

好的，以下是一个简单的VHDL代码，实现了一个下降沿触发、同步清零的十二进制计数器：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity counter is
    Port ( clk : in STD_LOGIC;
           rst : in STD_LOGIC;
           out_count : out STD_LOGIC_VECTOR (11 downto 0));
end counter;

architecture Behavioral of counter is
    signal count_reg : unsigned(11 downto 0);
begin
    process(clk, rst)
    begin
        if rst = '1' then -- 同步清零
            count_reg <= (others => '0');
        elsif rising_edge(clk) then -- 上升沿触发
            if count_reg = "101101100000" then -- 到达最大计数值
                count_reg <= (others => '0');
            else
                count_reg <= count_reg + 1; -- 计数器加1
            end if;
        end if;
    end process;
    
    out_count <= std_logic_vector(count_reg);
end Behavioral;

仿真代码：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity counter_tb is
end counter_tb;

architecture Behavioral of counter_tb is

    signal clk : std_logic := '0';
    signal rst : std_logic := '1';
    signal out_count : std_logic_vector(11 downto 0);
    
begin

    uut : entity work.counter
        port map(clk => clk,
                 rst => rst,
                 out_count => out_count);
                 
    clk_process : process
    begin
        clk <= '0';
        wait for 5 ns;
        clk <= '1';
        wait for 5 ns;
    end process;
    
    sim_process : process
    begin
        rst <= '1';
        wait for 10 ns;
        rst <= '0';
        wait for 10 ns;
        rst <= '1';
        wait for 10 ns;
        rst <= '0';
        wait for 10 ns;
        rst <= '1';
        wait for 10 ns;
        rst <= '0';
        wait;
    end process;
    
end Behavioral;

你可以使用任何支持VHDL的仿真工具来运行上面的代码，比如Xilinx ISE、Altera Quartus等。注意，这只是一个简单的实现，如果需要更高的性能或更复杂的功能，需要进一步优化和调整代码。