帮我写一个verilog语言的 25位计数器嵌套一个18位计数器,25位计数器输出到A 18位计数器输出到B 递增
时间: 2023-06-04 12:04:47 浏览: 53
好的,我可以为您写一个Verilog语言的25位计数器嵌套一个18位计数器,其中25位计数器的输出连接到A,18位计数器的输出连接到B,并且每次递增。以下是代码示例:
```verilog
module counter(
input clk,
input rst,
output reg [24:0] A,
output reg [17:0] B
);
reg [24:0] cnt_A;
reg [17:0] cnt_B;
always @(posedge clk or posedge rst) begin
if(rst) begin
cnt_A <= 25'h0;
cnt_B <= 18'h0;
end else begin
cnt_A <= cnt_A + 1;
cnt_B <= cnt_B + 1;
end
end
assign A = cnt_A;
assign B = cnt_B;
endmodule
```