写一个VHLD 三段式状态机

好的，以下是一个简单的VHDL三段式状态机的示例代码：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity three_stage_fsm is
    Port ( clk : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           input : in  STD_LOGIC;
           output : out  STD_LOGIC);
end three_stage_fsm;

architecture Behavioral of three_stage_fsm is
    type state_type is (state1, state2, state3);
    signal current_state, next_state : state_type;

begin
    process (clk, reset)
    begin
        if reset = '1' then
            current_state <= state1;
        elsif rising_edge(clk) then
            current_state <= next_state;
        end if;
    end process;

    process (current_state, input)
    begin
        case current_state is
            when state1 =>
                if input = '1' then
                    next_state <= state2;
                else
                    next_state <= state1;
                end if;
            when state2 =>
                next_state <= state3;
            when state3 =>
                next_state <= state1;
            when others =>
                next_state <= state1;
        end case;
    end process;

    process (current_state)
    begin
        case current_state is
            when state1 =>
                output <= '0';
            when state2 =>
                output <= '1';
            when state3 =>
                output <= '0';
            when others =>
                output <= '0';
        end case;
    end process;

end Behavioral;

这个状态机有三个状态：state1、state2和state3。输入信号为input，输出信号为output。在state1中，如果输入信号为1，则状态转移到state2；否则状态保持不变。在state2中，状态直接转移到state3。在state3中，状态转移到state1。在其他状态下，状态也转移到state1。这个状态机简单地实现了一个输入信号在连续三个时钟周期内保持高电平状态的功能。

希望这个例子能够帮助您编写VHDL三段式状态机。如果您还有其他问题，请随时问我。