module test; typedef struct packed { logic [9:-1][2:0] a; } ST1; typedef struct { ST1 st1; packed ST1 st2[]; logic [7:0] b; } ST4; initial begin ST4 st4; st4.st1.a[0][0] = 1; for (int i = 0; i < 5; i++) begin st4.st2.push_back(ST1'(i + 1)); end st4.b = 8'hAA; $display("%s", st4.st2); //CHECK-001:'{a:'h1}, st2:'{'a:'h1}, '{a:'h0},'{a:h1}}} end endmodule this piece of system verilog code, when compiled by vcs, it reports 1 error: Parsing design file'sc_assignment_pattern_030.sv' Error-[SE] Syntax error Following verilog source has syntax error: "sc_asssignment_pattern_030.sv", 21: token is 'packed' packed ST1 st2[]; System Verilog keyword 'packed' is not expected to be used in this context. How should I fix this error so that it can be compiled successfully by vcs?

The error message indicates that the use of 'packed' in the typedef declaration of 'st2' is incorrect. The 'packed' keyword is used to specify that a structure or union should be packed tightly in memory, but it cannot be used in the context of an array declaration.

To fix this error, you can remove the 'packed' keyword from the typedef declaration of 'st2'. The corrected code should look like:

module test;
  typedef struct packed {
    logic [9:-1][2:0] a;
  } ST1;

  typedef struct {
    ST1 st1;
    ST1 st2[];
    logic [7:0] b;
  } ST4;

  initial begin
    ST4 st4;
    st4.st1.a[0][0] = 1;
    for (int i = 0; i < 5; i++) begin
      st4.st2.push_back(ST1'(i + 1));
    end
    st4.b = 8'hAA;
    $display("%s", st4.st2); //CHECK-001:'{a:'h1}, st2:'{'a:'h1}, {'a:'h0},{'a:h1}}}
  end

endmodule

By removing the 'packed' keyword from the declaration of 'st2', the code should now compile without any syntax errors.