用verilog写一段CRC8校验算法的RTL代码

module CRC8_RTL(input [7:0] data, input clk, output reg [7:0] crc);
reg [7:0] CRC8_table = 8'h00, 8'h07, 8'h0e, 8'h09, 8'h1c, 8'h1b, 8'h12, 8'h15,
8'h38, 8'h3f, 8'h36, 8'h31, 8'h24, 8'h23, 8'h2a, 8'h2d;
reg [7:0] shift_reg;
reg [3:0] i; always @ (posedge clk) begin
shift_reg [7:1] <= shift_reg [6:0];
shift_reg [0] <= data[7];
crc <= CRC8_table[shift_reg]; for (i=0; i<8; i=i+1)
if (shift_reg[i] == 1'b1)
shift_reg[7:1] <= shift_reg[7:1] ^ CRC8_table[i];
end
endmodule