case语句实现一位半加器用Verilog HDL

module half_adder(A, B, SUM, CARRY);
input A, B;
output SUM, CARRY;

// case statement to implement half adder logic
case({A,B})
2'b00: begin
SUM = 1'b0;
CARRY = 1'b0;
end
2'b01: begin
SUM = 1'b1;
CARRY = 1'b0;
end
2'b10: begin
SUM = 1'b1;
CARRY = 1'b0;
end
2'b11: begin
SUM = 1'b0;
CARRY = 1'b1;
end
endcase
endmodule