fpga中使用verilog实现输入64个通道数据转换成一路数据输出，且输出时候给出当前输出的通道标识，每一个通道在64个周期内只有一个数据有效，根据64个vld判断数据的有效性。极限情况下，64个周期内64个通道都有数据，且不是按照通道序号连续的。 请给出实现的verilog程序

以下是一个可能的Verilog实现，该实现包括一个输入模块、一个输出模块和一个状态机模块，用于控制通道标识的输出：

module input_module (
    input clk,
    input [63:0] channel_data,
    input [63:0] vld,
    output reg [63:0] data_out,
    output reg [5:0] channel_id
);

reg [5:0] current_channel;
reg [63:0] current_data;
reg [63:0] valid_mask;

always @(posedge clk) begin
    valid_mask <= valid_mask | vld;
    if (valid_mask == 64'hFFFFFFFFFFFFFFFF) begin
        current_channel <= 0;
        current_data <= channel_data;
        valid_mask <= 0;
    end else begin
        current_channel <= current_channel + 1;
        current_data <= current_data | (vld & channel_data);
    end
end

assign data_out = current_data;
assign channel_id = current_channel;

endmodule


module output_module (
    input clk,
    input [63:0] data_in,
    input [5:0] channel_in,
    output reg [63:0] channel_data_out,
    output reg [63:0] vld_out
);

reg [5:0] current_channel;
reg [63:0] channel_data [0:63];
reg [63:0] vld [0:63];

always @(posedge clk) begin
    if (current_channel == 63) begin
        current_channel <= 0;
    end else begin
        current_channel <= current_channel + 1;
    end

    channel_data[current_channel] <= data_in;
    vld[current_channel] <= 64'h0000000000000001 << channel_in;
end

assign channel_data_out = channel_data[current_channel];
assign vld_out = vld[current_channel];

endmodule


module channel_id_fsm (
    input clk,
    input [5:0] channel_in,
    output reg [5:0] channel_out
);

reg [2:0] state;

always @(posedge clk) begin
    case (state)
        3'b000: begin
            channel_out <= channel_in;
            state <= 3'b001;
        end
        3'b001: begin
            state <= 3'b010;
        end
        3'b010: begin
            state <= 3'b100;
        end
        3'b100: begin
            channel_out <= 6'h00;
            state <= 3'b000;
        end
    endcase
end

endmodule

输入模块将64个通道的数据和有效性信号输入，并将其转换为单个数据输出和当前通道标识。输出模块将单个数据和当前通道标识输入，并将其存储在内部缓冲区中，以便在下一个时钟周期中输出。状态机模块则负责控制通道标识的输出，并确保在64个时钟周期内每个通道的数据都被输出一次。