module DW01_add_tb; // Declare inputs and outputs reg [3:0] A; reg [3:0] B; reg CI; wire [3:0] SUM; wire CO; // Instantiate design under test DW01_add dut( .A(A), .B(B), .CI(CI), .SUM(SUM), .CO(CO) ); // Initialize inputs initial begin A = 4'b0000; B = 4'b0000; CI = 0; end // Adder test case task test_adder; // Test case 1: 0 + 0 with carry-in of 0 A = 4'b0000; B = 4'b0000; CI = 0; #10; if (SUM !== 4'b0000 || CO !== 1'b0) $display("Test failed! 0 + 0 should be 0 with carry-out of 0"); // Test case 2: 7 + 3 with carry-in of 0 A = 4'b0111; B = 4'b0011; CI = 0; #10; if (SUM !== 4'b1010 || CO !== 1'b0) $display("Test failed! 7 + 3 should be 10 with carry-out of 0"); // Test case 3: 5 + 11 with carry-in of 1 A = 4'b0101; B = 4'b1011; CI = 1; #10; if (SUM !== 4'b0001 || CO !== 1'b1) $display("Test failed! 5 + 11 should be 16 with carry-out of 1"); // Test case 4: 15+15 with carry-in of 1 A = 4'b1111; B = 4'b1111; CI = 1; #10; if (SUM !== 4'b1110 || CO !== 1'b1) $display("Overflow!!!"); endtask // Run test cases initial begin test_adder(); $finish; end endmodule // DW01_add_tb If I want to add clock signal to this testbench, how should I modify the code?
时间: 2024-03-28 12:42:12 浏览: 16
To add a clock signal to this testbench, you can modify the code by declaring a clock signal as an input and using it to drive the testbench. Here's an example modification to the code:
```
module DW01_add_tb;
// Declare inputs and outputs
reg clk;
reg [3:0] A;
reg [3:0] B;
reg CI;
wire [3:0] SUM;
wire CO;
// Instantiate design under test
DW01_add dut(
.A(A),
.B(B),
.CI(CI),
.SUM(SUM),
.CO(CO)
);
// Initialize inputs
initial begin
A = 4'b0000;
B = 4'b0000;
CI = 0;
clk = 0;
end
// Add clock signal
always #5 clk = ~clk;
// Adder test case
task test_adder;
// Test case 1: 0 + 0 with carry-in of 0
A = 4'b0000;
B = 4'b0000;
CI = 0;
#10;
if (SUM !== 4'b0000 || CO !== 1'b0) $display("Test failed! 0 + 0 should be 0 with carry-out of 0");
// Test case 2: 7 + 3 with carry-in of 0
A = 4'b0111;
B = 4'b0011;
CI = 0;
#10;
if (SUM !== 4'b1010 || CO !== 1'b0) $display("Test failed! 7 + 3 should be 10 with carry-out of 0");
// Test case 3: 5 + 11 with carry-in of 1
A = 4'b0101;
B = 4'b1011;
CI = 1;
#10;
if (SUM !== 4'b0001 || CO !== 1'b1) $display("Test failed! 5 + 11 should be 16 with carry-out of 1");
// Test case 4: 15+15 with carry-in of 1
A = 4'b1111;
B = 4'b1111;
CI = 1;
#10;
if (SUM !== 4'b1110 || CO !== 1'b1) $display("Overflow!!!");
endtask
// Run test cases
initial begin
// Toggle clock signal
forever #5 clk = ~clk;
// Run test cases
test_adder();
$finish;
end
endmodule // DW01_add_tb
```
In this modified code, a clock signal `clk` is declared as an input and toggled every 5 time units using an `always` block. The test cases in the `test_adder` task can now be executed repeatedly using a `forever` loop that toggles the clock signal.