stm32f103c8t6如何使用pll达到最大系统时钟频率
时间: 2023-05-12 11:03:52 浏览: 142
STM32CubeMX配置STM32F103C8T6使用IAP升级
您可以使用以下代码来设置STM32F103C8T6的PLL以达到最大系统时钟频率:
```
RCC->CR |= RCC_CR_HSEON; // Enable HSE oscillator
while(!(RCC->CR & RCC_CR_HSERDY)); // Wait for HSE oscillator to stabilize
RCC->CFGR |= RCC_CFGR_PLLSRC_HSE; // Select HSE as PLL input source
RCC->CFGR &= ~RCC_CFGR_PLLMULL; // Clear PLLMULL bits
RCC->CFGR |= RCC_CFGR_PLLMULL9; // Set PLLMULL to 9 (for 72MHz)
RCC->CR |= RCC_CR_PLLON; // Enable PLL
while(!(RCC->CR & RCC_CR_PLLRDY)); // Wait for PLL to stabilize
FLASH->ACR |= FLASH_ACR_LATENCY_2; // Set flash latency to 2 wait states
RCC->CFGR |= RCC_CFGR_HPRE_DIV1; // Set AHB prescaler to 1
RCC->CFGR |= RCC_CFGR_PPRE1_DIV2; // Set APB1 prescaler to 2
RCC->CFGR |= RCC_CFGR_PPRE2_DIV1; // Set APB2 prescaler to 1
RCC->CFGR |= RCC_CFGR_SW_PLL; // Select PLL as system clock source
while((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL); // Wait for PLL to be selected as system clock source
```
这将使用外部高速晶体振荡器(HSE)作为PLL的输入源,并将PLL倍频器设置为9,以获得72MHz的系统时钟频率。此外,还设置了适当的AHB和APB分频器以确保系统时钟频率不超过72MHz。
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