Design-wide TNS

Design-wide TNS (Total Number of States) is a metric used in digital circuit design to measure the size and complexity of a design. It represents the total number of possible states that the circuit can be in.

TNS is an important factor in determining the feasibility of implementing a design on a particular technology node. As technology nodes shrink, the number of transistors that can be placed on a chip increases, which in turn increases the TNS of the design.

A high TNS can lead to longer simulation times and increased power consumption, as well as potential timing and routing issues. Therefore, designers must carefully consider TNS when designing circuits and may need to optimize their designs to reduce TNS and improve performance.