帮我用verilog写一个axi_slave协议，设计规格要求：系统时钟sysclk 为100Mhz，sysrstn为系统非同步复位,低电平有效，除sysrstn外，所有信号同步于时钟sysclk的上升沿，不用支持AXI Burst传输，不用支持Cache，Prot，Lock ，Wstrb功能。功能要求：AXI Slave Bus 通过内置的4个寄存器能响应AXI master 的读写操作，AXI 数据位宽为32bit，不用支持Narrow transfer。

module axi_slave (
input wire clk,
input wire rst_n,
input wire [31:0] awaddr,
input wire [2:0] awprot,
input wire awvalid,
output wire awready,
input wire [31:0] wdata,
input wire [3:0] wstrb,
input wire wvalid,
output wire wready,
output wire [1:0] bresp,
output wire bvalid,
input wire bready,
input wire [31:0] araddr,
input wire [2:0] arprot,
input wire arvalid,
output wire arready,
output wire [31:0] rdata,
output wire [1:0] rresp,
output wire rvalid,
input wire rready
);
reg [31:0] reg_0;
reg [31:0] reg_1;
reg [31:0] reg_2;
reg [31:0] reg_3;

reg [1:0] bresp_reg;
reg bvalid_reg;

reg [31:0] rdata_reg;
reg [1:0] rresp_reg;
reg rvalid_reg;

// Address write enable
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
reg_0 <= 32'h00000000;
reg_1 <= 32'h00000000;
reg_2 <= 32'h00000000;
reg_3 <= 32'h00000000;
end else begin
if (awvalid &amp;&amp; awready) begin
case (awaddr)
32'h00000000: reg_0 <= wdata;
32'h00000004: reg_1 <= wdata;
32'h00000008: reg_2 <= wdata;
32'h0000000C: reg_3 <= wdata;
endcase
end
end
end

// Write response
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
bresp_reg <= 2'b00;
bvalid_reg <= 1'b0;
end else begin
if (awvalid &amp;&amp; awready) begin
bvalid_reg <= 1'b1;
case (awaddr)
32'h00000000: bresp_reg <= 2'b00; // OKAY
32'h00000004: bresp_reg <= 2'b00; // OKAY
32'h00000008: bresp_reg <= 2'b00; // OKAY
32'h0000000C: bresp_reg <= 2'b00; // OKAY
default: bresp_reg <= 2'b10; // SLVERR
endcase
end else if (bready) begin
bvalid_reg <= 1'b0;
end
end
end

// Read address enable
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
rvalid_reg <= 1'b0;
rresp_reg <= 2'b00;
rdata_reg <= 32'h00000000;
end else begin
if (arvalid &amp;&amp; arready) begin
rvalid_reg <= 1'b1;
case (araddr)
32'h00000000: rdata_reg <= reg_0;
32'h00000004: rdata_reg <= reg_1;
32'h00000008: rdata_reg <= reg_2;
32'h0000000C: rdata_reg <= reg_3;
default: rresp_reg <= 2'b10; // SLVERR
endcase
end else if (rready) begin
rvalid_reg <= 1'b0;
end
end
end

// Assign outputs
assign awready = 1'b1;
assign wready = 1'b1;
assign bresp = bresp_reg;
assign bvalid = bvalid_reg;
assign arready = 1'b1;
assign rdata = rdata_reg;
assign rresp = rresp_reg;
assign rvalid = rvalid_reg;
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endmodule

这是一个简单的AXI Slave模块，根据您的设计规格进行了实现。它包含了4个32位的寄存器，可以响应AXI Master的读写操作。输出信号根据输入信号的状态和操作进行设置。请根据您的需求进行进一步的修改和调整。