用VHDL写一个包括时分秒的数字钟显示代码,其中包含在八个共阳数码管上显示数字,晶振的频率为5HZ,包括一个clk输入和一个分频信号clk1,数字钟的输入为clk1,clk为clk的5分频
时间: 2024-05-27 07:12:09 浏览: 90
entity digital_clock is
port(
clk : in std_logic;
clk1 : in std_logic;
seg : out std_logic_vector(7 downto 0);
an : out std_logic_vector(3 downto 0)
);
end entity digital_clock;
architecture Behavioral of digital_clock is
signal counter : integer range 0 to 49999999 := 0;
signal time : std_logic_vector(23 downto 0) := (others => '0');
signal digit : std_logic_vector(3 downto 0) := "1110";
signal seg_map : std_logic_vector(6 downto 0);
constant segments : std_logic_vector(0 to 9) := "1000000" & -- 0
"1111001" & -- 1
"0100100" & -- 2
"0110000" & -- 3
"0011001" & -- 4
"0010010" & -- 5
"0000010" & -- 6
"1111000" & -- 7
"0000000" & -- 8
"0010000"; -- 9
begin
seg_map <= segments(to_integer(unsigned(time(23 downto 20))));
process(clk1)
begin
if rising_edge(clk1) then
counter <= counter + 1;
if counter = 49999999 then
counter <= 0;
time <= time + "000000000001"; -- add one second
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
case digit is
when "1110" =>
seg <= seg_map(6 downto 0) & '1';
an <= "1110";
digit <= "1101";
when "1101" =>
seg <= seg_map(6 downto 0) & '1';
an <= "1101";
digit <= "1011";
when "1011" =>
seg <= seg_map(6 downto 0) & '1';
an <= "1011";
digit <= "0111";
when "0111" =>
seg <= seg_map(6 downto 0) & '1';
an <= "0111";
digit <= "1110";
end case;
end if;
end process;
end architecture Behavioral;