Error-[SE] Syntax error Following verilog source has syntax error : "./rtl/fifo.v", 2: token is 'parameter' parameter WIDTH = 32,

The Verilog code you provided indicates a syntax error on the second line of the file "./rtl/fifo.v". The error message states that the token "parameter" is causing the issue.

Without seeing the rest of the code, my best guess is that the parameter declaration is missing a semicolon at the end of the line. Here's an example of what the corrected line may look like:

parameter WIDTH = 32;

Make sure to check the rest of the code for any other syntax errors, as they may also be contributing to the issue.