[DRC UCIO-1] Unconstrained Logical Port: 8 out of 186 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: NAND_WE_N_2, NAND_CLE_1, NAND_WE_N_1, CLK_IN_D_0_clk_p[0], CLK_IN_D_0_clk_n[0], NAND_CE_N_0[0], NAND_ALE_0, and NAND_CLE_0.

这是一个 Vivado 设计规则检查的错误信息，提示设计中有 8 个逻辑端口没有位置约束，可能会导致 I/O 冲突或与电路板电源或连通性不兼容，影响性能、信号完整性，甚至可能会对设备或连接的组件造成损坏。要解决这个问题，需要指定所有引脚位置。如果不想指定未指定引脚位置，可以使用 set_property SEVERITY {Warning} [get_drc_checks UCIO-1] 命令允许位流生成。需要注意的是，当使用 Vivado Runs 基础设施时，需要将该命令添加到 .tcl 文件中，并将该文件作为实现运行的 write_bitstream 步骤的预钩子添加。出现问题的端口包括 NAND_WE_N_2、NAND_CLE_1、NAND_WE_N_1、CLK_IN_D_0_clk_p[0]、CLK_IN_D_0_clk_n[0]、NAND_CE_N_0[0]、NAND_ALE_0 和 NAND_CLE_0。

相关问题

[DRC UCIO-1] Unconstrained Logical Port: 4 out of 4 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: row[3:0].

这也是一个关于 FPGA 设计的报错信息，指出了该设计中有 4 个逻辑端口没有指定具体的位置约束（LOC），这可能会导致 I/O 冲突，与板子电源或连通性不兼容，影响性能和信号完整性，甚至在极端情况下可能会损坏设备或连接的元件。要纠正这个问题，需要指定所有端口的引脚位置。如果允许未指定引脚位置（不推荐），可以使用命令“set_property SEVERITY {Warning} [get_drc_checks UCIO-1]”生成比特流。报错信息指出了问题的端口是“row[3:0]”，需要在设计中指定这些端口的具体的位置约束（LOC）。

[DRC UCIO-1] Unconstrained Logical Port: 8 out of 139 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: USBIND_0_0_port_indctl[1:0], USBIND_0_0_vbus_pwrfault, USBIND_0_0_vbus_pwrselect, UART_0_0_rxd, UART_0_0_txd, FCLK_RESET0_N_0, and FCLK_CLK0_0.

这个问题看起来是一个警告信息，提示在设计中有一些逻辑端口没有指定物理引脚位置，可能会影响性能、信号完整性，甚至会导致设备损坏。为了纠正这个问题，需要指定所有的引脚位置。如果不想指定引脚位置，可以使用 set_property SEVERITY {Warning} [get_drc_checks UCIO-1] 命令生成位流文件，但这并不推荐。需要注意的是，对于使用 Vivado Runs 基础架构的设计，需要将这个命令添加到 .tcl 文件中，并将该文件作为 write_bitstream 步骤的前钩子。需要解决的逻辑端口包括 USBIND_0_0_port_indctl[1:0]、USBIND_0_0_vbus_pwrfault、USBIND_0_0_vbus_pwrselect、UART_0_0_rxd、UART_0_0_txd、FCLK_RESET0_N_0 和 FCLK_CLK0_0。