DMA读取DDR的设备树配置
时间: 2023-12-04 15:01:54 浏览: 75
基于Zynq 配置DMA在PS DDR 端和在PL AXI-Stream FIFODF
在设备树中配置DMA读取DDR需要做以下几步:
1. 配置DMA控制器节点
在设备树中配置一个DMA控制器节点,例如:
```
dma@f8003000 {
compatible = "xlnx,zynq-dma-1.00.a";
reg = <0xf8003000 0x1000>;
interrupts = <0 30 4>;
xlnx,device-id = <0x0>;
xlnx,include-sg ;
xlnx,sg-length-width = <0x10>;
dma-channel@40400000 {
compatible = "xlnx,axi-dma-mm2s-channel";
interrupts = <0 30 4>;
xlnx,datawidth = <0x20>;
xlnx,device-id = <0x0>;
xlnx,max-transfer-size = <0x800000>;
xlnx,sg-length-offset = <0x4>;
xlnx,scatter-gather-enable;
xlnx,include-dre;
};
};
```
2. 配置DDR控制器节点
在设备树中配置一个DDR控制器节点,例如:
```
ddr@3ed00000 {
compatible = "xlnx,zynq-ddr-3.10.a";
reg = <0x3ed00000 0x10000>;
clocks = <&clkc 12>;
clock-names = "ddrc";
phys = <&ps7_ddr_0>;
memory-controller {
device_type = "memory-controller";
reg = <0x0 0x10000>;
xlnx,ddr-phyclock-800mhz;
xlnx,ddr-num-ranks = <0x1>;
xlnx,ddr-memory-depth = <0x10000000>;
xlnx,ddr-row-width = <0x14>;
xlnx,ddr-bank-width = <0x3>;
xlnx,ddr-data-width = <0x40>;
xlnx,ddr-cas-latency = <0x4>;
xlnx,ddr-bank-groups = <0x1>;
xlnx,ddr-timing = <0x0000305a 0x00001d18 0x0000018e 0x00000030>;
xlnx,ddr-calibration = <0x0000016e 0x00000080 0x00000084>;
xlnx,ddr-device-id = <0x1>;
};
};
```
3. 配置DMA读取节点
在设备树中配置一个DMA读取节点,例如:
```
dma_read@43c00000 {
compatible = "xlnx,dma-read";
reg = <0x43c00000 0x10000>;
interrupts = <0 53 4>;
xlnx,device-id = <0x0>;
xlnx,dma-channel = <&dma 0>;
xlnx,ddr-address = <0x3ed00000>;
xlnx,ddr-length = <0x1000000>;
};
```
其中,`xlnx,dma-channel`属性需要指定DMA控制器节点中的DMA通道节点,`xlnx,ddr-address`属性需要指定DDR控制器节点的物理地址,`xlnx,ddr-length`属性需要指定读取的数据长度。
阅读全文