用VHDL编写数字正弦信号生成程序，正弦信号的参数为：幅度为5V，频率可调

，采样率为100MHz，信号长度为1000个采样点。

entity sin_wave is
Port ( clk : in STD_LOGIC;
sin_out : out STD_LOGIC_VECTOR (7 downto 0));
end sin_wave;

architecture Behavioral of sin_wave is
signal cnt : integer range 0 to 99 := 0;
signal phase : integer range 0 to 99 := 0;
signal sin_val : integer range -127 to 127 := 0;
signal freq_div : integer range 0 to 499 := 0;
signal FREQ : integer range 1 to 500 := 100; -- default frequency is 100Hz
signal sample_cnt : integer range 0 to 999 := 0;
begin
process(clk)
begin
if rising_edge(clk) then
cnt <= cnt + 1;
if cnt = 99 then
cnt <= 0;

freq_div <= freq_div + 1;
if freq_div = FREQ then
freq_div <= 0;
phase <= phase + 1;
if phase = 100 then
phase <= 0;
end if;
end if;

sin_val <= integer(round(127.0 * sin(2.0 * 3.141592653589793 * phase / 100.0)));

sample_cnt <= sample_cnt + 1;
if sample_cnt = 1000 then
sample_cnt <= 0;
end if;

end if;
end if;

if sample_cnt < 500 then
sin_out <= std_logic_vector(to_unsigned(127 + sin_val, 8));
else
sin_out <= std_logic_vector(to_unsigned(127 - sin_val, 8));
end if;

end process;

process(FREQ)
begin
FREQ <= FREQ / 10;
if FREQ = 0 then
FREQ <= 500;
end if;
end process;

end Behavioral;