用verilog实现一个SPI控制器，附带测试代码

好的，以下是一个简单的Verilog代码实现SPI控制器，以及一个测试代码：

module spi_controller (
  input clk,
  input reset_n,
  input enable,
  input [7:0] data_in,
  output [7:0] data_out,
  output reg shift_out,
  output reg busy
);

  parameter IDLE = 2'b00;
  parameter READ = 2'b01;
  parameter WRITE = 2'b10;

  reg [7:0] shift_reg;
  reg [1:0] state;
  reg [7:0] tx_data;
  reg [7:0] rx_data;
  reg [3:0] bit_count;

  always @(posedge clk or negedge reset_n) begin
    if (!reset_n) begin
      state <= IDLE;
      shift_reg <= 8'b0;
      tx_data <= 8'b0;
      rx_data <= 8'b0;
      shift_out <= 1'b0;
      bit_count <= 4'd0;
      busy <= 1'b0;
    end else if (enable) begin
      case (state)
        IDLE: begin
          if (enable) begin
            state <= WRITE;
            shift_reg <= {1'b1, tx_data};
            bit_count <= 4'd0;
            shift_out <= 1'b0;
            busy <= 1'b1;
          end
        end
        READ: begin
          if (bit_count == 4'd1) begin
            rx_data <= shift_reg[7:0];
            state <= IDLE;
            shift_out <= 1'b0;
            busy <= 1'b0;
          end else begin
            bit_count <= bit_count - 1;
            shift_reg <= {shift_reg[6:0], shift_out};
            shift_out <= shift_reg[7];
          end
        end
        WRITE: begin
          if (bit_count == 4'd7) begin
            state <= READ;
            bit_count <= 4'd4;
            shift_out <= 1'b0;
          end else begin
            bit_count <= bit_count + 1;
            shift_reg <= {shift_reg[6:0], shift_out};
            shift_out <= tx_data[bit_count];
          end
        end
      endcase
    end
  end

  assign data_out = rx_data;

  always @(posedge clk) begin
    if (enable && state == IDLE && !busy) begin
      tx_data <= data_in;
    end
  end

endmodule

测试代码：

module spi_controller_tb;

  reg clk;
  reg reset_n;
  reg enable;
  reg [7:0] data_in;
  wire [7:0] data_out;
  wire shift_out;
  wire busy;

  spi_controller dut (
    .clk(clk),
    .reset_n(reset_n),
    .enable(enable),
    .data_in(data_in),
    .data_out(data_out),
    .shift_out(shift_out),
    .busy(busy)
  );

  initial begin
    clk = 0;
    reset_n = 0;
    enable = 0;
    data_in = 0;

    #10 reset_n = 1;
    #10 enable = 1;
    data_in = 8'h55;
    #100 data_in = 8'hAA;
    #100 enable = 0;
    #100 enable = 1;
    data_in = 8'hFF;
    #100 $finish;
  end

  always #5 clk = ~clk;

endmodule

这个测试代码会在10ns之后使能spi控制器，并且将8位数据0x55发送给外部设备。在100ns之后，会重新使能spi控制器，并且发送0xAA，最后发送0xFF。你可以根据自己的需要修改测试代码。