[Place 30-689] Failed to place BITSLICE_CONTROL cell design_1_wrapper_i/design_1_i/nfc_8ch_v_wrapper_0/inst/nfc_ch2/efc_ip_wrapper/high_speed_selectio_wiz_0_inst/inst/top_inst/bs_ctrl_top_inst/BITSLICE_CTRL[7].bs_ctrl_inst on site BITSLICE_CONTROL_X0Y46 because Instance design_1_wrapper_i/design_1_i/nfc_8ch_v_wrapper_0/inst/nfc_ch2/efc_ip_wrapper/high_speed_selectio_wiz_0_inst/inst/top_inst/bs_ctrl_top_inst/BITSLICE_CTRL[7].bs_ctrl_inst can not be placed in CONTROL of site BITSLICE_CONTROL_X0Y46 because the bel is occupied by design_1_wrapper_i/design_1_i/nfc_8ch_v_wrapper_0/inst/nfc_ch0/efc_ip_wrapper/high_speed_selectio_wiz_re_inst/inst/top_inst/bs_ctrl_top_inst/BITSLICE_CTRL[6].bs_ctrl_inst(port:). This could be caused by bel constraint conflict. Please check if the cell is used correctly in the design.
时间: 2023-07-31 07:06:18 浏览: 1410
这是一个 FPGA 设计的错误信息,意思是在将设计映射到 FPGA 的时候,某个单元无法放置到指定位置上,因为该位置上的逻辑单元已经被占用了。这可能是因为位置约束出现了冲突,需要检查设计中的单元是否被正确使用,并且是否有其他约束限制了其位置。建议检查设计是否符合 FPGA 器件的规格要求,并且排除设计中可能存在的冲突。
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