[Place 30-689] Failed to place BITSLICE_CONTROL cell design_1_wrapper_i/design_1_i/nfc_8ch_v_wrapper_0/inst/nfc_ch2/efc_ip_wrapper/high_speed_selectio_wiz_0_inst/inst/top_inst/bs_ctrl_top_inst/BITSLICE_CTRL[7].bs_ctrl_inst on site BITSLICE_CONTROL_X0Y46 because Instance design_1_wrapper_i/design_1_i/nfc_8ch_v_wrapper_0/inst/nfc_ch2/efc_ip_wrapper/high_speed_selectio_wiz_0_inst/inst/top_inst/bs_ctrl_top_inst/BITSLICE_CTRL[7].bs_ctrl_inst can not be placed in CONTROL of site BITSLICE_CONTROL_X0Y46 because the bel is occupied by design_1_wrapper_i/design_1_i/nfc_8ch_v_wrapper_0/inst/nfc_ch0/efc_ip_wrapper/high_speed_selectio_wiz_re_inst/inst/top_inst/bs_ctrl_top_inst/BITSLICE_CTRL[6].bs_ctrl_inst(port:). This could be caused by bel constraint conflict. Please check if the cell is used correctly in the design.
时间: 2023-07-31 12:06:18 浏览: 902
这是一个 FPGA 设计的错误信息,意思是在将设计映射到 FPGA 的时候,某个单元无法放置到指定位置上,因为该位置上的逻辑单元已经被占用了。这可能是因为位置约束出现了冲突,需要检查设计中的单元是否被正确使用,并且是否有其他约束限制了其位置。建议检查设计是否符合 FPGA 器件的规格要求,并且排除设计中可能存在的冲突。
相关问题
[Constraints 18-1056] Clock 'dclk_200' completely overrides clock 'design_1_wrapper_i/design_1_i/clk_wiz_0/dclk_200'. New: create_generated_clock -name dclk_200 -source [get_pins design_1_wrapper_i/design_1_i/clk_wiz_0/clk_in1] -divide_by 1 -multiply_by 2 [get_pins design_1_wrapper_i/design_1_i/clk_wiz_0/dclk_200], ["/mnt/batman/ex_regions/yangang/zynq/bd_design/nfc_fm_20230610_8ch_125MHZ_syn_id5/project_1/project_1.srcs/constrs_1/new/top.xdc": and 46] Previous: create_generated_clock -source [get_pins design_1_wrapper_i/design_1_i/clk_wiz_0/clk_in1] -edges {1 2 3} -edge_shift {0.000 -2.656 -5.312} [get_pins design_1_wrapper_i/design_1_i/clk_wiz_0/dclk_200], ["/mnt/batman/ex_regions/yangang/zynq/bd_design/nfc_fm_20230610_8ch_125MHZ_syn_id5/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0_in_context.xdc": and 2]
这是一个关于 Vivado 约束文件的错误信息,指出了时钟 'dclk_200' 被新的约束完全覆盖了,新约束为:
create_generated_clock -name dclk_200 -source [get_pins design_1_wrapper_i/design_1_i/clk_wiz_0/clk_in1] -divide_by 1 -multiply_by 2 [get_pins design_1_wrapper_i/design_1_i/clk_wiz_0/dclk_200]
而之前的约束为:
create_generated_clock -source [get_pins design_1_wrapper_i/design_1_i/clk_wiz_0/clk_in1] -edges {1 2 3} -edge_shift {0.000 -2.656 -5.312} [get_pins design_1_wrapper_i/design_1_i/clk_wiz_0/dclk_200]
这种情况通常是由于在约束文件中出现了重复的约束或者约束冲突导致的。建议检查约束文件中的所有时钟约束,并确保每个时钟都只有一个约束,并且没有冲突。可以选择删除一个约束或者修改约束参数来解决问题。
create_generated_clock -name ldpc_clk -source [get_pins design_1_wrapper_i/design_1_i/clk_wiz_1/clk_in1] -divide_by 3 -multiply_by 2 [get_pins design_1_wrapper_i/design_1_i/clk_wiz_1/ldpc_clk]
你似乎在询问一个命令,这是一个时钟生成命令,用于创建一个新的时钟信号。该命令的作用是创建一个名为 ldpc_clk 的时钟信号,其源时钟为 design_1_wrapper_i/design_1_i/clk_wiz_1/clk_in1,将其分频系数设置为 3,倍频系数设置为 2,并将其输出到 design_1_wrapper_i/design_1_i/clk_wiz_1/ldpc_clk 这个引脚上。