简易 38 译码器设计 VERILOG

module decoder_38(input [2:0] A, output reg [37:0] Y);

always @(*) begin
case(A)
3'b000: Y = 38'b0000000000000000000000000000000000000001;
3'b001: Y = 38'b0000000000000000000000000000000000000010;
3'b010: Y = 38'b0000000000000000000000000000000000000100;
3'b011: Y = 38'b0000000000000000000000000000000000001000;
3'b100: Y = 38'b0000000000000000000000000000000000010000;
3'b101: Y = 38'b0000000000000000000000000000000000100000;
3'b110: Y = 38'b0000000000000000000000000000000001000000;
3'b111: Y = 38'b0000000000000000000000000000000010000000;
default: Y = 38'b0000000000000000000000000000000000000000;
endcase
end

endmodule