设计一个具有异步复位控制的 4bits 十进制同步加法计数器,采用按键 BTND 作为时钟输入,通过防抖处理后作为计数器的时钟信号。计数器的 计数结果通过七段数码管显示,写出verilog代码和xdc文件
时间: 2024-05-15 09:16:48 浏览: 2
Verilog 代码:
```verilog
module counter(
input wire clk,
input wire rst,
input wire btn_d,
output reg [3:0] cnt,
output reg [6:0] seg
);
reg [3:0] next_cnt;
reg [2:0] digit;
parameter [9:0] DIGIT_DELAY = 5000;
always @(posedge clk or posedge rst) begin
if(rst) begin
next_cnt <= 4'b0000;
cnt <= 4'b0000;
seg <= 7'b111_1111;
digit <= 3'b000;
end
else if(btn_d) begin
next_cnt <= cnt + 1;
end
end
always @(posedge clk or posedge rst) begin
if(rst) begin
digit <= 3'b000;
end
else begin
case(digit)
3'b000: begin
seg <= 7'b011_1111;
cnt[0] ? (seg <= 7'b000_0110) : (seg <= 7'b011_1111);
digit <= 3'b001;
end
3'b001: begin
seg <= 7'b101_1111;
cnt[1] ? (seg <= 7'b000_0110) : (seg <= 7'b011_1111);
digit <= 3'b010;
end
3'b010: begin
seg <= 7'b110_1111;
cnt[2] ? (seg <= 7'b000_0110) : (seg <= 7'b011_1111);
digit <= 3'b011;
end
3'b011: begin
seg <= 7'b111_0111;
cnt[3] ? (seg <= 7'b000_0110) : (seg <= 7'b011_1111);
digit <= 3'b000;
end
endcase
end
end
always @(posedge clk) begin
if(rst) begin
cnt <= 4'b0000;
end
else if(btn_d) begin
cnt <= next_cnt;
end
end
endmodule
```
XDC 文件:
```
set_property -dict {PACKAGE_PIN P107 IOSTANDARD LVCMOS33} [get_ports btn_d]
set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS33} [get_ports {clk}]
set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports {seg[0]}]
set_property -dict {PACKAGE_PIN R10 IOSTANDARD LVCMOS33} [get_ports {seg[1]}]
set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS33} [get_ports {seg[2]}]
set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS33} [get_ports {seg[3]}]
set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports {seg[4]}]
set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS33} [get_ports {seg[5]}]
set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS33} [get_ports {seg[6]}]
set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS33} [get_ports {dp}]
set_property -dict {PACKAGE_PIN T9 IOSTANDARD LVCMOS33} [get_ports {an[0]}]
set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVCMOS33} [get_ports {an[1]}]
set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS33} [get_ports {an[2]}]
set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS33} [get_ports {an[3]}]
```