Verilog语言七人表决器代码及测试代码

以下是Verilog语言实现七人表决器的代码：

module voter (
    input [6:0] in,
    output reg out
);

wire [6:0] in_and;
wire [6:0] in_or;

assign in_and = ∈
assign in_or = |in;

always @(in_and, in_or)
begin
    if (in_and == 7'b111_1111) // all voters voted
        out = 1;
    else if (in_or == 7'b000_0000) // no voters voted
        out = 0;
    else
        out = 1'bZ; // still waiting for more votes
end

endmodule

以下是七人表决器的测试代码：

module voter_tb;

reg [6:0] in;
wire out;

voter dut (
    .in(in),
    .out(out)
);

initial begin
    #10 in = 7'b000_0001; // voter 1 voted
    #10 in = 7'b000_0011; // voters 1 and 2 voted
    #10 in = 7'b000_0111; // voters 1, 2, and 3 voted
    #10 in = 7'b000_1111; // voters 1, 2, 3, and 4 voted
    #10 in = 7'b001_1111; // voters 1, 2, 3, 4, and 5 voted
    #10 in = 7'b011_1111; // voters 1, 2, 3, 4, 5, and 6 voted
    #10 in = 7'b111_1111; // all voters voted
end

endmodule

在测试代码中，每次改变`in`的值代表有新的选民进行表决。当所有选民都进行了表决时，`out`的值将变为1。如果没有选民进行了表决，则`out`的值将变为0。如果仍有选民没有进行表决，则`out`的值将为高阻态。