wildcard in makefile

In Makefiles, a wildcard is a character or sequence of characters that represents one or more other characters. It is often used to match file names or patterns.

The most common use of wildcards in Makefiles is with the "wildcard" function. The syntax of the "wildcard" function is as follows:

$(wildcard pattern)

This function expands to a space-separated list of all the file names that match the given pattern. For example, to get a list of all the C source files in the current directory, you could use:

C_FILES := $(wildcard *.c)

This would set the variable "C_FILES" to a space-separated list of all the files in the current directory that end with ".c".

Another way to use wildcards in Makefiles is with pattern rules. Pattern rules are used to define a rule for building a set of files that match a particular pattern. For example:

%.o: %.c
    $(CC) $(CFLAGS) -c $< -o $@

This rule tells Make to build any file with the ".o" extension that corresponds to a file with the ".c" extension. The "$<" and "$@" variables are used to represent the input and output files, respectively.

Overall, wildcards are a powerful feature of Makefiles that allow you to write more generic rules and automate your build process.