分别用状态机一段式、两段式、三段式的方式描述Mealy型检测序列器检测1011，写出Verilog代码

以下是针对Mealy型检测序列器检测1011的Verilog代码，分别采用一段式、两段式、三段式状态机描述方式。

1. 一段式状态机

module seq_detector(input clk, input reset, input bit sequence_in, output bit detected);
    reg [1:0] state;
    
    parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11;
    
    always @(posedge clk or negedge reset) begin
        if (reset == 1'b0) begin
            state <= S0;
        end else begin
            case (state)
                S0: begin
                    if (sequence_in == 1'b1) begin
                        state <= S1;
                    end else begin
                        state <= S0;
                    end
                end
                S1: begin
                    if (sequence_in == 1'b0) begin
                        state <= S2;
                    end else begin
                        state <= S1;
                    end
                end
                S2: begin
                    if (sequence_in == 1'b1) begin
                        state <= S3;
                    end else begin
                        state <= S0;
                    end
                end
                S3: begin
                    state <= S3;
                end
            endcase
        end
    end
    
    assign detected = (state == S3) ? 1'b1 : 1'b0;
endmodule

2. 两段式状态机

module seq_detector(input clk, input reset, input bit sequence_in, output bit detected);
    reg [1:0] state;
    
    parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11;
    
    always @(posedge clk or negedge reset) begin
        if (reset == 1'b0) begin
            state <= S0;
        end else begin
            case (state)
                S0: begin
                    if (sequence_in == 1'b1) begin
                        state <= S1;
                    end else begin
                        state <= S0;
                    end
                end
                S1: begin
                    if (sequence_in == 1'b0) begin
                        state <= S2;
                    end else begin
                        state <= S1;
                    end
                end
                S2: begin
                    if (sequence_in == 1'b1) begin
                        state <= S3;
                    end else begin
                        state <= S0;
                    end
                end
                S3: begin
                    if (sequence_in == 1'b1) begin
                        state <= S4;
                    end else begin
                        state <= S3;
                    end
                end
                S4: begin
                    if (sequence_in == 1'b0) begin
                        state <= S5;
                    end else begin
                        state <= S4;
                    end
                end
                S5: begin
                    state <= S5;
                end
            endcase
        end
    end
    
    assign detected = (state == S5) ? 1'b1 : 1'b0;
endmodule

3. 三段式状态机

module seq_detector(input clk, input reset, input bit sequence_in, output bit detected);
    reg [2:0] state;
    
    parameter S0 = 3'b000, S1 = 3'b001, S2 = 3'b010, S3 = 3'b011, S4 = 3'b100, S5 = 3'b101, S6 = 3'b110;
    
    always @(posedge clk or negedge reset) begin
        if (reset == 1'b0) begin
            state <= S0;
        end else begin
            case (state)
                S0: begin
                    if (sequence_in == 1'b1) begin
                        state <= S1;
                    end else begin
                        state <= S0;
                    end
                end
                S1: begin
                    if (sequence_in == 1'b0) begin
                        state <= S2;
                    end else begin
                        state <= S1;
                    end
                end
                S2: begin
                    if (sequence_in == 1'b1) begin
                        state <= S3;
                    end else begin
                        state <= S0;
                    end
                end
                S3: begin
                    if (sequence_in == 1'b1) begin
                        state <= S4;
                    end else begin
                        state <= S3;
                    end
                end
                S4: begin
                    if (sequence_in == 1'b0) begin
                        state <= S5;
                    end else begin
                        state <= S4;
                    end
                end
                S5: begin
                    if (sequence_in == 1'b0) begin
                        state <= S5;
                    end else if (sequence_in == 1'b1) begin
                        state <= S6;
                    end
                end
                S6: begin
                    state <= S6;
                end
            endcase
        end
    end
    
    assign detected = (state == S5) ? 1'b1 : 1'b0;
endmodule